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author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:14:49 +0300 |
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committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-25 17:13:53 +0300 |
commit | 673d8215415dc0c13e96b8d757102d942916d1b2 (patch) | |
tree | ce6ec6398c83f100750e826d9b4bee7d9e4f9353 /tests | |
parent | cced0d653973f6ad0d9e8bdbd365e12d0f2316f9 (diff) | |
download | qemu-673d8215415dc0c13e96b8d757102d942916d1b2.zip qemu-673d8215415dc0c13e96b8d757102d942916d1b2.tar.gz qemu-673d8215415dc0c13e96b8d757102d942916d1b2.tar.bz2 |
arm: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tests')
-rw-r--r-- | tests/tcg/aarch64/gdbstub/test-sve.py | 2 | ||||
-rw-r--r-- | tests/tcg/aarch64/sme-outprod1.c | 2 | ||||
-rw-r--r-- | tests/tcg/aarch64/system/boot.S | 6 | ||||
-rw-r--r-- | tests/tcg/aarch64/system/semiheap.c | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/tests/tcg/aarch64/gdbstub/test-sve.py b/tests/tcg/aarch64/gdbstub/test-sve.py index b96bdbb..ef57c74 100644 --- a/tests/tcg/aarch64/gdbstub/test-sve.py +++ b/tests/tcg/aarch64/gdbstub/test-sve.py @@ -1,6 +1,6 @@ from __future__ import print_function # -# Test the SVE registers are visable and changeable via gdbstub +# Test the SVE registers are visible and changeable via gdbstub # # This is launched via tests/guest-debug/run-test.py # diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c index 6e5972d..0c814ed 100644 --- a/tests/tcg/aarch64/sme-outprod1.c +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -28,7 +28,7 @@ asm( " fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" /* * Read the first 4x4 sub-matrix of elements from tile 1: - * Note that za1h should be interchangable here. + * Note that za1h should be interchangeable here. */ " mov w12, #0\n" " mova z0.s, p0/m, za1v.s[w12, #0]\n" diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S index f136363..501685d 100644 --- a/tests/tcg/aarch64/system/boot.S +++ b/tests/tcg/aarch64/system/boot.S @@ -9,7 +9,7 @@ /* * Semihosting interface on ARM AArch64 - * See "Semihosting for AArch32 and AArch64 Relase 2.0" by ARM + * See "Semihosting for AArch32 and AArch64 Release 2.0" by ARM * w0 - semihosting call number * x1 - semihosting parameter */ @@ -147,7 +147,7 @@ __start: * T0SZ[5:0] = 2^(64 - 25) * * The size of T0SZ controls what the initial lookup level. It - * would be nice to start at level 2 but unfortunatly for a + * would be nice to start at level 2 but unfortunately for a * flat-mapping on the virt machine we need to handle IA's * with at least 1gb range to see RAM. So we start with a * level 1 lookup. @@ -189,7 +189,7 @@ __start: msr cpacr_el1, x0 /* Setup some stack space and enter the test code. - * Assume everthing except the return value is garbage when we + * Assume everything except the return value is garbage when we * return, we won't need it. */ adrp x0, stack_end diff --git a/tests/tcg/aarch64/system/semiheap.c b/tests/tcg/aarch64/system/semiheap.c index 693a1b0..1a8c0f3 100644 --- a/tests/tcg/aarch64/system/semiheap.c +++ b/tests/tcg/aarch64/system/semiheap.c @@ -86,7 +86,7 @@ int main(int argc, char *argv[argc]) } ptr_to_heap++; } - ml_printf("r/w to heap upto %p\n", ptr_to_heap); + ml_printf("r/w to heap up to %p\n", ptr_to_heap); ml_printf("Passed HeapInfo checks\n"); return 0; |