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| author | Paolo Bonzini <pbonzini@redhat.com> | 2022-10-19 14:01:36 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-10-20 15:16:13 +0200 |
| commit | 314d3eff66f41f39191aaca2e5f6e3dc81480c1b (patch) | |
| tree | 0ad5c97909f2530e794e70151d651bbe9e2573ac /tests | |
| parent | 0d4bcac3cac461798d810e6df54768d9613ea794 (diff) | |
| download | qemu-314d3eff66f41f39191aaca2e5f6e3dc81480c1b.zip qemu-314d3eff66f41f39191aaca2e5f6e3dc81480c1b.tar.gz qemu-314d3eff66f41f39191aaca2e5f6e3dc81480c1b.tar.bz2 | |
target/i386: introduce function to set rounding mode from FPCW or MXCSR bits
VROUND, FSTCW and STMXCSR all have to perform the same conversion from
x86 rounding modes to softfloat constants. Since the ISA is consistent
on the meaning of the two-bit rounding modes, extract the common code
into a wrapper for set_float_rounding_mode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tests')
0 files changed, 0 insertions, 0 deletions