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authorMax Filippov <jcmvbkbc@gmail.com>2019-02-18 07:15:10 -0800
committerMax Filippov <jcmvbkbc@gmail.com>2019-02-28 04:43:23 -0800
commit00988da4860c363522daa39709cb5985d6a6033a (patch)
tree480c2ccfdf9943f3fbdf3302cf17bf3c3f9bbba4 /tests
parent9b2d08a066b85315fa41a3bbe8cc2186278c0f79 (diff)
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tests/tcg/xtensa: conditionalize and fix s32c1i tests
Make s32c1i tests conditional on the presence of this option. Initialize ATOMCTL SR when it's present to allow RCW transactions on uncached memory. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests')
-rw-r--r--tests/tcg/xtensa/test_s32c1i.S12
1 files changed, 12 insertions, 0 deletions
diff --git a/tests/tcg/xtensa/test_s32c1i.S b/tests/tcg/xtensa/test_s32c1i.S
index 93b575d..2885d9d 100644
--- a/tests/tcg/xtensa/test_s32c1i.S
+++ b/tests/tcg/xtensa/test_s32c1i.S
@@ -2,7 +2,13 @@
test_suite s32c1i
+#if XCHAL_HAVE_S32C1I
+
test s32c1i_nowrite
+#if XCHAL_HW_VERSION >= 230000
+ movi a2, 0x29
+ wsr a2, atomctl
+#endif
movi a2, 1f
movi a3, 1
wsr a3, scompare1
@@ -20,6 +26,10 @@ test s32c1i_nowrite
test_end
test s32c1i_write
+#if XCHAL_HW_VERSION >= 230000
+ movi a2, 0x29
+ wsr a2, atomctl
+#endif
movi a2, 1f
movi a3, 3
wsr a3, scompare1
@@ -36,4 +46,6 @@ test s32c1i_write
.text
test_end
+#endif
+
test_suite_end