qtest: add libqos including PCI support

This includes basic PCI support for the PC platform.  Enough
abstraction should be present to support non-PC platforms too.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Message-id: 1366123521-4330-3-git-send-email-aliguori@us.ibm.com

4 files changed, 490 insertions, 0 deletions

diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c
new file mode 100644
index 0000000..3bde8ab
--- /dev/null
+++ b/tests/libqos/pci-pc.c
@@ -0,0 +1,239 @@
+/*
+ * libqos PCI bindings for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ *  Anthony Liguori   <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqtest.h"
+#include "libqos/pci-pc.h"
+
+#include "hw/pci/pci_regs.h"
+
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include <glib.h>
+
+typedef struct QPCIBusPC
+{
+    QPCIBus bus;
+
+    uint32_t pci_hole_start;
+    uint32_t pci_hole_size;
+    uint32_t pci_hole_alloc;
+
+    uint16_t pci_iohole_start;
+    uint16_t pci_iohole_size;
+    uint16_t pci_iohole_alloc;
+} QPCIBusPC;
+
+static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint8_t value;
+
+    if (port < 0x10000) {
+        value = inb(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint16_t value;
+
+    if (port < 0x10000) {
+        value = inw(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
+{
+    uintptr_t port = (uintptr_t)addr;
+    uint32_t value;
+
+    if (port < 0x10000) {
+        value = inl(port);
+    } else {
+        memread(port, &value, sizeof(value));
+    }
+
+    return value;
+}
+
+static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outb(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outw(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
+{
+    uintptr_t port = (uintptr_t)addr;
+
+    if (port < 0x10000) {
+        outl(port, value);
+    } else {
+        memwrite(port, &value, sizeof(value));
+    }
+}
+
+static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inb(0xcfc);
+}
+
+static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inw(0xcfc);
+}
+
+static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    return inl(0xcfc);
+}
+
+static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outb(0xcfc, value);
+}
+
+static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outw(0xcfc, value);
+}
+
+static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
+{
+    outl(0xcf8, (1 << 31) | (devfn << 8) | offset);
+    outl(0xcfc, value);
+}
+
+static void *qpci_pc_iomap(QPCIBus *bus, QPCIDevice *dev, int barno)
+{
+    QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
+    static const int bar_reg_map[] = {
+        PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_1, PCI_BASE_ADDRESS_2,
+        PCI_BASE_ADDRESS_3, PCI_BASE_ADDRESS_4, PCI_BASE_ADDRESS_5,
+    };
+    int bar_reg;
+    uint32_t addr;
+    uint64_t size;
+    uint32_t io_type;
+
+    g_assert(barno >= 0 && barno <= 5);
+    bar_reg = bar_reg_map[barno];
+
+    qpci_config_writel(dev, bar_reg, 0xFFFFFFFF);
+    addr = qpci_config_readl(dev, bar_reg);
+
+    io_type = addr & PCI_BASE_ADDRESS_SPACE;
+    if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
+        addr &= PCI_BASE_ADDRESS_IO_MASK;
+    } else {
+        addr &= PCI_BASE_ADDRESS_MEM_MASK;
+    }
+
+    size = (1ULL << ctzl(addr));
+    if (size == 0) {
+        return NULL;
+    }
+
+    if (io_type == PCI_BASE_ADDRESS_SPACE_IO) {
+        uint16_t loc;
+
+        g_assert((s->pci_iohole_alloc + size) <= s->pci_iohole_size);
+        loc = s->pci_iohole_start + s->pci_iohole_alloc;
+        s->pci_iohole_alloc += size;
+
+        qpci_config_writel(dev, bar_reg, loc | PCI_BASE_ADDRESS_SPACE_IO);
+
+        return (void *)(intptr_t)loc;
+    } else {
+        uint64_t loc;
+
+        g_assert((s->pci_hole_alloc + size) <= s->pci_hole_size);
+        loc = s->pci_hole_start + s->pci_hole_alloc;
+        s->pci_hole_alloc += size;
+
+        qpci_config_writel(dev, bar_reg, loc);
+
+        return (void *)(intptr_t)loc;
+    }
+}
+
+static void qpci_pc_iounmap(QPCIBus *bus, void *data)
+{
+    /* FIXME */
+}
+
+QPCIBus *qpci_init_pc(void)
+{
+    QPCIBusPC *ret;
+
+    ret = g_malloc(sizeof(*ret));
+
+    ret->bus.io_readb = qpci_pc_io_readb;
+    ret->bus.io_readw = qpci_pc_io_readw;
+    ret->bus.io_readl = qpci_pc_io_readl;
+
+    ret->bus.io_writeb = qpci_pc_io_writeb;
+    ret->bus.io_writew = qpci_pc_io_writew;
+    ret->bus.io_writel = qpci_pc_io_writel;
+
+    ret->bus.config_readb = qpci_pc_config_readb;
+    ret->bus.config_readw = qpci_pc_config_readw;
+    ret->bus.config_readl = qpci_pc_config_readl;
+
+    ret->bus.config_writeb = qpci_pc_config_writeb;
+    ret->bus.config_writew = qpci_pc_config_writew;
+    ret->bus.config_writel = qpci_pc_config_writel;
+
+    ret->bus.iomap = qpci_pc_iomap;
+    ret->bus.iounmap = qpci_pc_iounmap;
+
+    ret->pci_hole_start = 0xE0000000;
+    ret->pci_hole_size = 0x20000000;
+    ret->pci_hole_alloc = 0;
+
+    ret->pci_iohole_start = 0xc000;
+    ret->pci_iohole_size = 0x4000;
+    ret->pci_iohole_alloc = 0;
+
+    return &ret->bus;
+}
diff --git a/tests/libqos/pci-pc.h b/tests/libqos/pci-pc.h
new file mode 100644
index 0000000..4f7475f
--- /dev/null
+++ b/tests/libqos/pci-pc.h
@@ -0,0 +1,20 @@
+/*
+ * libqos PCI bindings for PC
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ *  Anthony Liguori   <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_PCI_PC_H
+#define LIBQOS_PCI_PC_H
+
+#include "libqos/pci.h"
+
+QPCIBus *qpci_init_pc(void);
+
+#endif
diff --git a/tests/libqos/pci.c b/tests/libqos/pci.c
new file mode 100644
index 0000000..95e287b
--- /dev/null
+++ b/tests/libqos/pci.c
@@ -0,0 +1,151 @@
+/*
+ * libqos PCI bindings
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ *  Anthony Liguori   <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "libqos/pci.h"
+
+#include "hw/pci/pci_regs.h"
+#include <glib.h>
+
+#include <stdio.h>
+
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+                         void (*func)(QPCIDevice *dev, int devfn, void *data),
+                         void *data)
+{
+    int slot;
+
+    for (slot = 0; slot < 32; slot++) {
+        int fn;
+
+        for (fn = 0; fn < 8; fn++) {
+            QPCIDevice *dev;
+
+            dev = qpci_device_find(bus, QPCI_DEVFN(slot, fn));
+            if (!dev) {
+                continue;
+            }
+
+            if (vendor_id != -1 &&
+                qpci_config_readw(dev, PCI_VENDOR_ID) != vendor_id) {
+                continue;
+            }
+
+            if (device_id != -1 &&
+                qpci_config_readw(dev, PCI_DEVICE_ID) != device_id) {
+                continue;
+            }
+
+            func(dev, QPCI_DEVFN(slot, fn), data);
+        }
+    }
+}
+
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn)
+{
+    QPCIDevice *dev;
+
+    dev = g_malloc0(sizeof(*dev));
+    dev->bus = bus;
+    dev->devfn = devfn;
+
+    if (qpci_config_readw(dev, PCI_VENDOR_ID) == 0xFFFF) {
+        g_free(dev);
+        return NULL;
+    }
+
+    return dev;
+}
+
+void qpci_device_enable(QPCIDevice *dev)
+{
+    uint16_t cmd;
+
+    /* FIXME -- does this need to be a bus callout? */
+    cmd = qpci_config_readw(dev, PCI_COMMAND);
+    cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+    qpci_config_writew(dev, PCI_COMMAND, cmd);
+}
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readb(dev->bus, dev->devfn, offset);
+}
+
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readw(dev->bus, dev->devfn, offset);
+}
+
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset)
+{
+    return dev->bus->config_readl(dev->bus, dev->devfn, offset);
+}
+
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value)
+{
+    dev->bus->config_writeb(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value)
+{
+    dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
+{
+    dev->bus->config_writew(dev->bus, dev->devfn, offset, value);
+}
+
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readb(dev->bus, data);
+}
+
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readw(dev->bus, data);
+}
+
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
+{
+    return dev->bus->io_readl(dev->bus, data);
+}
+
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
+{
+    dev->bus->io_writeb(dev->bus, data, value);
+}
+
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
+{
+    dev->bus->io_writew(dev->bus, data, value);
+}
+
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
+{
+    dev->bus->io_writel(dev->bus, data, value);
+}
+
+void *qpci_iomap(QPCIDevice *dev, int barno)
+{
+    return dev->bus->iomap(dev->bus, dev, barno);
+}
+
+void qpci_iounmap(QPCIDevice *dev, void *data)
+{
+    dev->bus->iounmap(dev->bus, data);
+}
+
+
diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h
new file mode 100644
index 0000000..3439431
--- /dev/null
+++ b/tests/libqos/pci.h
@@ -0,0 +1,80 @@
+/*
+ * libqos PCI bindings
+ *
+ * Copyright IBM, Corp. 2012-2013
+ *
+ * Authors:
+ *  Anthony Liguori   <aliguori@us.ibm.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef LIBQOS_PCI_H
+#define LIBQOS_PCI_H
+
+#include <stdint.h>
+
+#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
+
+typedef struct QPCIDevice QPCIDevice;
+typedef struct QPCIBus QPCIBus;
+
+struct QPCIBus
+{
+    uint8_t (*io_readb)(QPCIBus *bus, void *addr);
+    uint16_t (*io_readw)(QPCIBus *bus, void *addr);
+    uint32_t (*io_readl)(QPCIBus *bus, void *addr);
+
+    void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
+    void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
+    void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
+
+    uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
+    uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
+    uint32_t (*config_readl)(QPCIBus *bus, int devfn, uint8_t offset);
+
+    void (*config_writeb)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint8_t value);
+    void (*config_writew)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint16_t value);
+    void (*config_writel)(QPCIBus *bus, int devfn,
+                          uint8_t offset, uint32_t value);
+
+    void *(*iomap)(QPCIBus *bus, QPCIDevice *dev, int barno);
+    void (*iounmap)(QPCIBus *bus, void *data);
+};
+
+struct QPCIDevice
+{
+    QPCIBus *bus;
+    int devfn;
+};
+
+void qpci_device_foreach(QPCIBus *bus, int vendor_id, int device_id,
+                         void (*func)(QPCIDevice *dev, int devfn, void *data),
+                         void *data);
+QPCIDevice *qpci_device_find(QPCIBus *bus, int devfn);
+
+void qpci_device_enable(QPCIDevice *dev);
+
+uint8_t qpci_config_readb(QPCIDevice *dev, uint8_t offset);
+uint16_t qpci_config_readw(QPCIDevice *dev, uint8_t offset);
+uint32_t qpci_config_readl(QPCIDevice *dev, uint8_t offset);
+
+void qpci_config_writeb(QPCIDevice *dev, uint8_t offset, uint8_t value);
+void qpci_config_writew(QPCIDevice *dev, uint8_t offset, uint16_t value);
+void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value);
+
+uint8_t qpci_io_readb(QPCIDevice *dev, void *data);
+uint16_t qpci_io_readw(QPCIDevice *dev, void *data);
+uint32_t qpci_io_readl(QPCIDevice *dev, void *data);
+
+void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value);
+void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value);
+void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value);
+
+void *qpci_iomap(QPCIDevice *dev, int barno);
+void qpci_iounmap(QPCIDevice *dev, void *data);
+
+#endif