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authorRichard Henderson <rth@twiddle.net>2013-03-28 05:37:55 +0000
committerStefan Weil <sw@weilnetz.de>2013-04-11 19:58:21 +0200
commitee79c356ffe18eea90ea4bbde2057cebe6bb654f (patch)
treea7666d3485225c6a5bd9378b464bbf91fff2a983 /tci.c
parent4699ca6dbf335b0c38e291a530c6ad85e599253d (diff)
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tci: Make tcg temporaries local to tcg_qemu_tb_exec
We're moving away from the temporaries stored in env. Make sure we can differentiate between temp stores and possibly bogus stores for extra call arguments. Move TCG_AREG0 and TCG_REG_CALL_STACK out of the way of the parameter passing registers. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off by: Stefan Weil <sw@weilnetz.de>
Diffstat (limited to 'tci.c')
-rw-r--r--tci.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/tci.c b/tci.c
index 70f8308..c742c8d 100644
--- a/tci.c
+++ b/tci.c
@@ -112,6 +112,7 @@ static void tci_write_reg(TCGReg index, tcg_target_ulong value)
{
assert(index < ARRAY_SIZE(tci_reg));
assert(index != TCG_AREG0);
+ assert(index != TCG_REG_CALL_STACK);
tci_reg[index] = value;
}
@@ -435,9 +436,12 @@ static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
/* Interpret pseudo code in tb. */
tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
{
+ long tcg_temps[CPU_TEMP_BUF_NLONGS];
+ uintptr_t sp_value = (uintptr_t)(tcg_temps + CPU_TEMP_BUF_NLONGS);
tcg_target_ulong next_tb = 0;
tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
+ tci_reg[TCG_REG_CALL_STACK] = sp_value;
assert(tb_ptr);
for (;;) {
@@ -585,6 +589,7 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t0 = tci_read_r32(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
+ assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint32_t *)(t1 + t2) = t0;
break;
@@ -869,6 +874,7 @@ tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr)
t0 = tci_read_r64(&tb_ptr);
t1 = tci_read_r(&tb_ptr);
t2 = tci_read_s32(&tb_ptr);
+ assert(t1 != sp_value || (int32_t)t2 < 0);
*(uint64_t *)(t1 + t2) = t0;
break;