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| author | Richard Henderson <rth@twiddle.net> | 2010-01-07 10:07:35 -0800 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-06 17:14:24 +0100 |
| commit | a38e609c46e751f30277db6b3c07a3321c5c1d2a (patch) | |
| tree | 87a79017dbca243e720fd89c4a850740b6ea498b /tcg | |
| parent | fd7a446f162768c044b3bf3844f7605eeef351af (diff) | |
| download | qemu-a38e609c46e751f30277db6b3c07a3321c5c1d2a.zip qemu-a38e609c46e751f30277db6b3c07a3321c5c1d2a.tar.gz qemu-a38e609c46e751f30277db6b3c07a3321c5c1d2a.tar.bz2 | |
tcg: document double-word support opcodes.
The internal opcodes brcond2, add2, sub2, mulu2 were undocumented.
Place these in a new section that clearly indicates that they are
not to be emitted by translators.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/README | 23 |
1 files changed, 23 insertions, 0 deletions
@@ -323,6 +323,29 @@ st32_i64 t0, t1, offset write(t0, t1 + offset) Write 8, 16, 32 or 64 bits to host memory. +********* 64-bit target on 32-bit host support + +The following opcodes are internal to TCG. Thus they are to be implemented by +32-bit host code generators, but are not to be emitted by guest translators. +They are emitted as needed by inline functions within "tcg-op.h". + +* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label + +Similar to brcond, except that the 64-bit values T0 and T1 +are formed from two 32-bit arguments. + +* add2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high +* sub2_i32 t0_low, t0_high, t1_low, t1_high, t2_low, t2_high + +Similar to add/sub, except that the 64-bit inputs T1 and T2 are +formed from two 32-bit arguments, and the 64-bit output T0 +is returned in two 32-bit outputs. + +* mulu2_i32 t0_low, t0_high, t1, t2 + +Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding +the full 64-bit product T0. The later is returned in two 32-bit outputs. + ********* QEMU specific operations * tb_exit t0 |