diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-04-02 15:09:52 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-04-15 20:09:53 +0200 |
| commit | 6995a4a063d3ab3ceb21aad8c8a78f4cfc5e4140 (patch) | |
| tree | 65d627810ba09d8dcbb796836b5e5048ba7a7f52 /tcg | |
| parent | 991041a4eb8895390d816375021dccfd12c81752 (diff) | |
| download | qemu-6995a4a063d3ab3ceb21aad8c8a78f4cfc5e4140.zip qemu-6995a4a063d3ab3ceb21aad8c8a78f4cfc5e4140.tar.gz qemu-6995a4a063d3ab3ceb21aad8c8a78f4cfc5e4140.tar.bz2 | |
tcg-ppc64: Use MFOCRF instead of MFCR
It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 70cbb86..c7800b0 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -382,6 +382,7 @@ static int tcg_target_const_match (tcg_target_long val, #define SRAWI XO31(824) #define NEG XO31(104) #define MFCR XO31( 19) +#define MFOCRF (MFCR | (1u << 20)) #define NOR XO31(124) #define CNTLZW XO31( 26) #define CNTLZD XO31( 58) @@ -430,6 +431,7 @@ static int tcg_target_const_match (tcg_target_long val, #define ME(e) ((e)<<1) #define BO(o) ((o)<<21) #define MB64(b) ((b)<<5) +#define FXM(b) (1 << (19 - (b))) #define LK 1 @@ -1226,10 +1228,12 @@ static void tcg_out_setcond (TCGContext *s, TCGType type, TCGCond cond, sh = 31; crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT); crtest: - tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type); - if (crop) tcg_out32 (s, crop); - tcg_out32 (s, MFCR | RT (0)); - tcg_out_rlw(s, RLWINM, arg0, 0, sh, 31, 31); + tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); + if (crop) { + tcg_out32(s, crop); + } + tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); + tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); break; default: |