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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-09-05 12:37:36 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-04 11:50:11 -0700 |
| commit | 4fcd301707ccc656f27e3dc324cdbe20122a9740 (patch) | |
| tree | 9085f92d291f88c057bbd552ce937d5b03e09bcc /tcg | |
| parent | 752b17693e7af43ba77cee59eb9a1ec6966b3ded (diff) | |
| download | qemu-4fcd301707ccc656f27e3dc324cdbe20122a9740.zip qemu-4fcd301707ccc656f27e3dc324cdbe20122a9740.tar.gz qemu-4fcd301707ccc656f27e3dc324cdbe20122a9740.tar.bz2 | |
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
This is saturating add and subtract, signed and unsigned.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/arm/tcg-target.c.inc | 24 | ||||
| -rw-r--r-- | tcg/arm/tcg-target.h | 2 |
2 files changed, 25 insertions, 1 deletions
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index b94e6ed..f0cfed7 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -184,6 +184,10 @@ typedef enum { INSN_VORR = 0xf2200110, INSN_VSUB = 0xf3000800, INSN_VMUL = 0xf2000910, + INSN_VQADD = 0xf2000010, + INSN_VQADD_U = 0xf3000010, + INSN_VQSUB = 0xf2000210, + INSN_VQSUB_U = 0xf3000210, INSN_VABS = 0xf3b10300, INSN_VMVN = 0xf3b00580, @@ -2396,7 +2400,11 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) case INDEX_op_dup2_vec: case INDEX_op_add_vec: case INDEX_op_mul_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: case INDEX_op_sub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: case INDEX_op_xor_vec: return C_O1_I2(w, w, w); case INDEX_op_or_vec: @@ -2763,6 +2771,18 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_sub_vec: tcg_out_vreg3(s, INSN_VSUB, q, vece, a0, a1, a2); return; + case INDEX_op_ssadd_vec: + tcg_out_vreg3(s, INSN_VQADD, q, vece, a0, a1, a2); + return; + case INDEX_op_sssub_vec: + tcg_out_vreg3(s, INSN_VQSUB, q, vece, a0, a1, a2); + return; + case INDEX_op_usadd_vec: + tcg_out_vreg3(s, INSN_VQADD_U, q, vece, a0, a1, a2); + return; + case INDEX_op_ussub_vec: + tcg_out_vreg3(s, INSN_VQSUB_U, q, vece, a0, a1, a2); + return; case INDEX_op_xor_vec: tcg_out_vreg3(s, INSN_VEOR, q, 0, a0, a1, a2); return; @@ -2873,6 +2893,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) case INDEX_op_shli_vec: case INDEX_op_shri_vec: case INDEX_op_sari_vec: + case INDEX_op_ssadd_vec: + case INDEX_op_sssub_vec: + case INDEX_op_usadd_vec: + case INDEX_op_ussub_vec: return 1; case INDEX_op_abs_vec: case INDEX_op_cmp_vec: diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 94d768f..71621f2 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -167,7 +167,7 @@ extern bool use_neon_instructions; #define TCG_TARGET_HAS_shs_vec 0 #define TCG_TARGET_HAS_shv_vec 0 #define TCG_TARGET_HAS_mul_vec 1 -#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_sat_vec 1 #define TCG_TARGET_HAS_minmax_vec 0 #define TCG_TARGET_HAS_bitsel_vec 0 #define TCG_TARGET_HAS_cmpsel_vec 0 |