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| author | Andreas Färber <afaerber@suse.de> | 2012-05-09 19:26:59 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-05-09 13:59:19 -0500 |
| commit | 1b3e76ebd1e270eae27e502ea8b836c31d95f801 (patch) | |
| tree | d188f22e55a414021dce10507638d42d335ebd92 /tcg | |
| parent | a082615b0752e113e40537e7f820ffb4bbb15750 (diff) | |
| download | qemu-1b3e76ebd1e270eae27e502ea8b836c31d95f801.zip qemu-1b3e76ebd1e270eae27e502ea8b836c31d95f801.tar.gz qemu-1b3e76ebd1e270eae27e502ea8b836c31d95f801.tar.bz2 | |
tcg/ppc: Fix CONFIG_TCG_PASS_AREG0 mode
Adjust the tcg_out_qemu_{ld,st}() slow paths to pass AREG0 in r3,
based on patches by malc.
Also adjust the registers clobbered, based on patch by Alex.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Alexander Graf <agraf@suse.de>
[AF: Do not hardcode r3 for AREG0, requested by Alex]
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/ppc/tcg-target.c | 33 |
1 files changed, 32 insertions, 1 deletions
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 20888e2..4cde48d 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -244,9 +244,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) tcg_regset_set32(ct->u.regs, 0, 0xffffffff); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); +#if TARGET_LONG_BITS == 64 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#endif +#endif +#else /* !AREG0 */ #if TARGET_LONG_BITS == 64 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); #endif +#endif break; case 'K': /* qemu_st[8..32] constraint */ ct->ct |= TCG_CT_REG; @@ -254,9 +264,19 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); +#if TARGET_LONG_BITS == 64 + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); +#endif +#endif +#else /* !AREG0 */ #if TARGET_LONG_BITS == 64 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); #endif +#endif break; case 'M': /* qemu_st64 constraint */ ct->ct |= TCG_CT_REG; @@ -266,6 +286,12 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); tcg_regset_reset_reg(ct->u.regs, TCG_REG_R7); +#if defined(CONFIG_TCG_PASS_AREG0) + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R8); +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + tcg_regset_reset_reg(ct->u.regs, TCG_REG_R9); +#endif +#endif break; #else case 'L': @@ -512,7 +538,6 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) #include "../../softmmu_defs.h" #ifdef CONFIG_TCG_PASS_AREG0 -#error CONFIG_TCG_PASS_AREG0 is not supported /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, int mmu_idx) */ static const void * const qemu_ld_helpers[4] = { @@ -618,6 +643,9 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) /* slow path */ ir = 3; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); +#endif #if TARGET_LONG_BITS == 32 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #else @@ -817,6 +845,9 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) /* slow path */ ir = 3; +#ifdef CONFIG_TCG_PASS_AREG0 + tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); +#endif #if TARGET_LONG_BITS == 32 tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); #else |