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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-04-06 10:48:03 -0700 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2020-04-07 16:19:49 +0100 |
| commit | cce743abbf398a324879039cd582349b36da0ea6 (patch) | |
| tree | 34af0a0b182a9e086e75fde1a3f72a11308c5b0c /tcg | |
| parent | eca7a8e6c08f80129ae0bab7d060da568ed90f20 (diff) | |
| download | qemu-cce743abbf398a324879039cd582349b36da0ea6.zip qemu-cce743abbf398a324879039cd582349b36da0ea6.tar.gz qemu-cce743abbf398a324879039cd582349b36da0ea6.tar.bz2 | |
tcg/i386: Fix %r12 guest_base initialization
When %gs cannot be used, we use register offset addressing.
This path is almost never used, so it was clearly not tested.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200406174803.8192-1-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/i386/tcg-target.inc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index 7f61eee..ec083bd 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3737,7 +3737,7 @@ static void tcg_target_qemu_prologue(TCGContext *s) } else { /* Choose R12 because, as a base, it requires a SIB byte. */ x86_guest_base_index = TCG_REG_R12; - tcg_out_mov(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); + tcg_out_movi(s, TCG_TYPE_PTR, x86_guest_base_index, guest_base); tcg_regset_set_reg(s->reserved_regs, x86_guest_base_index); } } |