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authorRichard Henderson <richard.henderson@linaro.org>2021-01-27 19:21:10 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-02-05 10:24:14 -1000
commit9592e8974f364daa372247c9240fd9e08b70c2ac (patch)
treeb8fd697f48716af457390e5f7c429289148a2d5f /tcg
parentcbec0754bed0d890a277746c68ce193cd3f1070d (diff)
downloadqemu-9592e8974f364daa372247c9240fd9e08b70c2ac.zip
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tcg/tci: Inline tci_write_reg32s into the only caller
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/tci.c10
1 files changed, 1 insertions, 9 deletions
diff --git a/tcg/tci.c b/tcg/tci.c
index c3a8511..e8023b5 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -117,14 +117,6 @@ tci_write_reg(tcg_target_ulong *regs, TCGReg index, tcg_target_ulong value)
regs[index] = value;
}
-#if TCG_TARGET_REG_BITS == 64
-static void
-tci_write_reg32s(tcg_target_ulong *regs, TCGReg index, int32_t value)
-{
- tci_write_reg(regs, index, value);
-}
-#endif
-
static void tci_write_reg8(tcg_target_ulong *regs, TCGReg index, uint8_t value)
{
tci_write_reg(regs, index, value);
@@ -907,7 +899,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
t0 = *tb_ptr++;
t1 = tci_read_r(regs, &tb_ptr);
t2 = tci_read_s32(&tb_ptr);
- tci_write_reg32s(regs, t0, *(int32_t *)(t1 + t2));
+ tci_write_reg(regs, t0, *(int32_t *)(t1 + t2));
break;
case INDEX_op_ld_i64:
t0 = *tb_ptr++;