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authorRichard Henderson <richard.henderson@linaro.org>2017-09-11 12:44:30 -0700
committerRichard Henderson <richard.henderson@linaro.org>2017-09-17 06:52:19 -0700
commitf46934df662182097dce07d57ec00f37e4d2abf1 (patch)
tree17cb6113bf3f6e248669ba4aa813fa8eb222b883 /tcg/tci
parent07ddf036fa66bca279590c09fe1c46bcdcc5bcff (diff)
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tcg: Remove tcg_regset_set32
It's not even clear what the interface REG and VAL32 were supposed to mean. All uses had REG = 0 and VAL32 was the bitset assigned to the destination. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci')
-rw-r--r--tcg/tci/tcg-target.inc.c11
1 files changed, 4 insertions, 7 deletions
diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.inc.c
index f964433..913c380 100644
--- a/tcg/tci/tcg-target.inc.c
+++ b/tcg/tci/tcg-target.inc.c
@@ -390,7 +390,7 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* qemu_ld constraint */
case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG;
- tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
+ ct->u.regs = BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
return NULL;
@@ -870,14 +870,11 @@ static void tcg_target_init(TCGContext *s)
tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX);
/* Registers available for 32 bit operations. */
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
- BIT(TCG_TARGET_NB_REGS) - 1);
+ tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1;
/* Registers available for 64 bit operations. */
- tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
- BIT(TCG_TARGET_NB_REGS) - 1);
+ tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1;
/* TODO: Which registers should be set here? */
- tcg_regset_set32(tcg_target_call_clobber_regs, 0,
- BIT(TCG_TARGET_NB_REGS) - 1);
+ tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1;
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);