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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-31 23:26:14 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-19 08:51:11 -0700 |
| commit | baa94c0d333b5eccd68450625e0c3960e85d1913 (patch) | |
| tree | 3e23d7ae84c975e1c85913fcce42dccdbf16af1e /tcg/tci | |
| parent | 7b7d8b2d9a7fd68de821f96267e224c1a6256af1 (diff) | |
| download | qemu-baa94c0d333b5eccd68450625e0c3960e85d1913.zip qemu-baa94c0d333b5eccd68450625e0c3960e85d1913.tar.gz qemu-baa94c0d333b5eccd68450625e0c3960e85d1913.tar.bz2 | |
tcg/tci: Reserve r13 for a temporary
We're about to adjust the offset range on host memory ops,
and the format of branches. Both will require a temporary.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci')
| -rw-r--r-- | tcg/tci/tcg-target.c.inc | 1 | ||||
| -rw-r--r-- | tcg/tci/tcg-target.h | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index fa3de99..5269a78 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -820,6 +820,7 @@ static void tcg_target_init(TCGContext *s) MAKE_64BIT_MASK(TCG_REG_R0, 64 / TCG_TARGET_REG_BITS); s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); /* The call arguments come first, followed by the temp storage. */ diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index f2e5cba..80cafb7 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -156,6 +156,7 @@ typedef enum { TCG_REG_R14, TCG_REG_R15, + TCG_REG_TMP = TCG_REG_R13, TCG_AREG0 = TCG_REG_R14, TCG_REG_CALL_STACK = TCG_REG_R15, } TCGReg; |