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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-02-02 17:21:27 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-19 11:08:00 -0700 |
| commit | f6db0d8dc63e0ae3668646653ffa1c5be16fbe5e (patch) | |
| tree | 34fb439645a665451fa7f033faad8a555c8293cb /tcg/tci/tcg-target.c.inc | |
| parent | 5255f48c1c8c39be8ad95ef7ec0da0557924c806 (diff) | |
| download | qemu-f6db0d8dc63e0ae3668646653ffa1c5be16fbe5e.zip qemu-f6db0d8dc63e0ae3668646653ffa1c5be16fbe5e.tar.gz qemu-f6db0d8dc63e0ae3668646653ffa1c5be16fbe5e.tar.bz2 | |
tcg/tci: Implement mulu2, muls2
We already had mulu2_i32 for a 32-bit host; expand this to 64-bit
hosts as well. The muls2_i32 and the 64-bit opcodes are new.
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci/tcg-target.c.inc')
| -rw-r--r-- | tcg/tci/tcg-target.c.inc | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 69f4165..e48dbc9 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -141,9 +141,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) return C_O2_I4(r, r, r, r, r, r); case INDEX_op_brcond2_i32: return C_O0_I4(r, r, r, r); +#endif + case INDEX_op_mulu2_i32: + case INDEX_op_mulu2_i64: + case INDEX_op_muls2_i32: + case INDEX_op_muls2_i64: return C_O2_I2(r, r, r, r); -#endif case INDEX_op_movcond_i32: case INDEX_op_movcond_i64: @@ -434,7 +438,6 @@ static void tcg_out_op_rrrrr(TCGContext *s, TCGOpcode op, TCGReg r0, tcg_out32(s, insn); } -#if TCG_TARGET_REG_BITS == 32 static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3) { @@ -447,7 +450,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op, insn = deposit32(insn, 20, 4, r3); tcg_out32(s, insn); } -#endif static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1, TCGReg r2, @@ -726,10 +728,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2], args[3], args[4]); tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5])); break; - case INDEX_op_mulu2_i32: +#endif + + CASE_32_64(mulu2) + CASE_32_64(muls2) tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]); break; -#endif case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_st_i32: |