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author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-28 14:54:16 -1000 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
commit | 187f44d9da0ca8ac08451f03f62b259080596570 (patch) | |
tree | 690efddf00e1b64d7b373d78c55ef37728317142 /tcg/tci/tcg-target.c.inc | |
parent | f6ff97ab565d4aa779ae3e07e8c5f13e7495a005 (diff) | |
download | qemu-187f44d9da0ca8ac08451f03f62b259080596570.zip qemu-187f44d9da0ca8ac08451f03f62b259080596570.tar.gz qemu-187f44d9da0ca8ac08451f03f62b259080596570.tar.bz2 |
tcg/tci: Restrict TCG_TARGET_NB_REGS to 16
As noted in several comments, 8 regs is not enough for 32-bit
to perform calls, as currently implemented. Shortly, we will
rearrange the encoding which will make 32 regs impossible.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci/tcg-target.c.inc')
-rw-r--r-- | tcg/tci/tcg-target.c.inc | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 3327ce3..7e3bed8 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -187,7 +187,6 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, -#if TCG_TARGET_NB_REGS >= 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, @@ -196,7 +195,6 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, -#endif }; #if MAX_OPC_PARAM_IARGS != 6 @@ -216,15 +214,11 @@ static const int tcg_target_call_iarg_regs[] = { #if TCG_TARGET_REG_BITS == 32 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ TCG_REG_R7, -#if TCG_TARGET_NB_REGS >= 16 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, TCG_REG_R12, -#else -# error Too few input registers available -#endif #endif }; @@ -245,7 +239,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "r05", "r06", "r07", -#if TCG_TARGET_NB_REGS >= 16 "r08", "r09", "r10", @@ -254,25 +247,6 @@ static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "r13", "r14", "r15", -#if TCG_TARGET_NB_REGS >= 32 - "r16", - "r17", - "r18", - "r19", - "r20", - "r21", - "r22", - "r23", - "r24", - "r25", - "r26", - "r27", - "r28", - "r29", - "r30", - "r31" -#endif -#endif }; #endif |