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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-01-27 20:30:00 -1000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-02-05 10:24:14 -1000 |
| commit | ae40c098ac637b51ccf350d70765e76129b838a5 (patch) | |
| tree | 07165bc1f82aae7671785e1edc220cab22ad0221 /tcg/tci.c | |
| parent | 7abd007cbc145c1f3745c6b1ca0deea2ef5c8591 (diff) | |
| download | qemu-ae40c098ac637b51ccf350d70765e76129b838a5.zip qemu-ae40c098ac637b51ccf350d70765e76129b838a5.tar.gz qemu-ae40c098ac637b51ccf350d70765e76129b838a5.tar.bz2 | |
tcg/tci: Implement 64-bit division
Trivially implemented like other arithmetic.
Tested via check-tcg and the ppc64 target.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci.c')
| -rw-r--r-- | tcg/tci.c | 22 |
1 files changed, 19 insertions, 3 deletions
@@ -894,14 +894,30 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, t2 = tci_read_ri64(regs, &tb_ptr); tci_write_reg(regs, t0, t1 * t2); break; -#if TCG_TARGET_HAS_div_i64 case INDEX_op_div_i64: + t0 = *tb_ptr++; + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (int64_t)t1 / (int64_t)t2); + break; case INDEX_op_divu_i64: + t0 = *tb_ptr++; + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint64_t)t1 / (uint64_t)t2); + break; case INDEX_op_rem_i64: + t0 = *tb_ptr++; + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (int64_t)t1 % (int64_t)t2); + break; case INDEX_op_remu_i64: - TODO(); + t0 = *tb_ptr++; + t1 = tci_read_ri64(regs, &tb_ptr); + t2 = tci_read_ri64(regs, &tb_ptr); + tci_write_reg(regs, t0, (uint64_t)t1 % (uint64_t)t2); break; -#endif case INDEX_op_and_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(regs, &tb_ptr); |