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| author | Richard Henderson <richard.henderson@linaro.org> | 2017-12-13 16:52:57 -0600 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2017-12-29 12:43:40 -0800 |
| commit | 1df3caa946e08b387511dfba3a37d78910e51796 (patch) | |
| tree | 2ece3af901a3571120c0f2747ef6d213e45a2049 /tcg/tci.c | |
| parent | 923ed1750186591b04d7d61399f6d68b4e0608f2 (diff) | |
| download | qemu-1df3caa946e08b387511dfba3a37d78910e51796.zip qemu-1df3caa946e08b387511dfba3a37d78910e51796.tar.gz qemu-1df3caa946e08b387511dfba3a37d78910e51796.tar.bz2 | |
tcg: Allow 6 arguments to TCG helpers
We already handle this in the backends, and the lifetime datum
for the TCGOp is already large enough.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tci.c')
| -rw-r--r-- | tcg/tci.c | 12 |
1 files changed, 8 insertions, 4 deletions
@@ -40,7 +40,7 @@ tcg_abort(); \ } while (0) -#if MAX_OPC_PARAM_IARGS != 5 +#if MAX_OPC_PARAM_IARGS != 6 # error Fix needed, number of supported input arguments changed! #endif #if TCG_TARGET_REG_BITS == 32 @@ -48,11 +48,12 @@ typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, + tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong); #else typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, tcg_target_ulong, - tcg_target_ulong); + tcg_target_ulong, tcg_target_ulong); #endif static tcg_target_ulong tci_read_reg(const tcg_target_ulong *regs, TCGReg index) @@ -520,7 +521,9 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tci_read_reg(regs, TCG_REG_R7), tci_read_reg(regs, TCG_REG_R8), tci_read_reg(regs, TCG_REG_R9), - tci_read_reg(regs, TCG_REG_R10)); + tci_read_reg(regs, TCG_REG_R10), + tci_read_reg(regs, TCG_REG_R11), + tci_read_reg(regs, TCG_REG_R12)); tci_write_reg(regs, TCG_REG_R0, tmp64); tci_write_reg(regs, TCG_REG_R1, tmp64 >> 32); #else @@ -528,7 +531,8 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tci_read_reg(regs, TCG_REG_R1), tci_read_reg(regs, TCG_REG_R2), tci_read_reg(regs, TCG_REG_R3), - tci_read_reg(regs, TCG_REG_R5)); + tci_read_reg(regs, TCG_REG_R5), + tci_read_reg(regs, TCG_REG_R6)); tci_write_reg(regs, TCG_REG_R0, tmp64); #endif break; |