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authorPeter Maydell <peter.maydell@linaro.org>2014-02-20 15:02:06 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-02-20 15:02:07 +0000
commit3d2bb5cc81ca52dcff854172625a3bb33987495c (patch)
tree464c866b0d1337bb232669cbdb7591880926ff20 /tcg/tcg.c
parent61e8a923646903d76a6d952019716b417d42eedc (diff)
parent6399ab3325b7d4f77441c8a00fa9dae98bb0ac43 (diff)
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Merge remote-tracking branch 'remotes/rth/tcg-next' into staging
* remotes/rth/tcg-next: tcg/i386: Use SHLX/SHRX/SARX instructions tcg/i386: Use ANDN instruction tcg/i386: Add tcg_out_vex_modrm tcg/i386: Move TCG_CT_CONST_* to tcg-target.c disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX tcg/optimize: Add more identity simplifications tcg/optimize: Optmize ANDC X,Y,Y to MOV X,0 tcg/optimize: Simply some logical ops to NOT tcg/optimize: Handle known-zeros masks for ANDC tcg/optimize: add known-zero bits compute for load ops tcg/optimize: improve known-zero bits for 32-bit ops tcg/optimize: fix known-zero bits optimization tcg/optimize: fix known-zero bits for right shift ops tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1]. TCG: Fix 32-bit host allocation typo Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/tcg.c')
-rw-r--r--tcg/tcg.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/tcg.c b/tcg/tcg.c
index acd02b9..ffc851e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -526,7 +526,7 @@ static inline int tcg_temp_new_internal(TCGType type, int temp_local)
ts->temp_local = temp_local;
ts->name = NULL;
ts++;
- ts->base_type = TCG_TYPE_I32;
+ ts->base_type = type;
ts->type = TCG_TYPE_I32;
ts->temp_allocated = 1;
ts->temp_local = temp_local;