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author | Richard Henderson <rth@twiddle.net> | 2011-10-27 14:15:00 -0700 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2011-10-30 09:06:23 +0000 |
commit | df072774cb0175c1ae93af18c6e1f54624831b7e (patch) | |
tree | 110de7b288b7d54d2b5e7dd7635bb42aa1205497 /tcg/tcg-op.h | |
parent | 7999f7e1273b63ec3a60d8cf2cb79cb88575744a (diff) | |
download | qemu-df072774cb0175c1ae93af18c6e1f54624831b7e.zip qemu-df072774cb0175c1ae93af18c6e1f54624831b7e.tar.gz qemu-df072774cb0175c1ae93af18c6e1f54624831b7e.tar.bz2 |
tcg: Optimize some forms of deposit.
If the deposit replaces the entire word, optimize to a move.
If we're inserting to the top of the word, avoid the mask of arg2
as we'll be shifting out all of the garbage and shifting in zeros.
If the host is 32-bit, reduce a 64-bit deposit to a 32-bit deposit
when possible.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/tcg-op.h')
-rw-r--r-- | tcg/tcg-op.h | 65 |
1 files changed, 51 insertions, 14 deletions
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index fea5983..24ec7fc 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2045,38 +2045,75 @@ static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { + uint32_t mask; + TCGv_i32 t1; + + if (ofs == 0 && len == 32) { + tcg_gen_mov_i32(ret, arg2); + return; + } if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); - } else { - uint32_t mask = (1u << len) - 1; - TCGv_i32 t1 = tcg_temp_new_i32 (); + return; + } + + mask = (1u << len) - 1; + t1 = tcg_temp_new_i32(); + if (ofs + len < 32) { tcg_gen_andi_i32(t1, arg2, mask); tcg_gen_shli_i32(t1, t1, ofs); - tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i32(ret, ret, t1); - - tcg_temp_free_i32(t1); + } else { + tcg_gen_shli_i32(t1, arg2, ofs); } + tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); + tcg_gen_or_i32(ret, ret, t1); + + tcg_temp_free_i32(t1); } static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { + uint64_t mask; + TCGv_i64 t1; + + if (ofs == 0 && len == 64) { + tcg_gen_mov_i64(ret, arg2); + return; + } if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); - } else { - uint64_t mask = (1ull << len) - 1; - TCGv_i64 t1 = tcg_temp_new_i64 (); + return; + } +#if TCG_TARGET_REG_BITS == 32 + if (ofs >= 32) { + tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), + TCGV_LOW(arg2), ofs - 32, len); + return; + } + if (ofs + len <= 32) { + tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1), + TCGV_LOW(arg2), ofs, len); + return; + } +#endif + + mask = (1ull << len) - 1; + t1 = tcg_temp_new_i64(); + + if (ofs + len < 64) { tcg_gen_andi_i64(t1, arg2, mask); tcg_gen_shli_i64(t1, t1, ofs); - tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); - tcg_gen_or_i64(ret, ret, t1); - - tcg_temp_free_i64(t1); + } else { + tcg_gen_shli_i64(t1, arg2, ofs); } + tcg_gen_andi_i64(ret, arg1, ~(mask << ofs)); + tcg_gen_or_i64(ret, ret, t1); + + tcg_temp_free_i64(t1); } /***************************************/ |