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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-04-30 11:02:23 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-05-22 15:09:43 -0400 |
| commit | 38dc12947ec9106237f9cdbd428792c985cd86ae (patch) | |
| tree | e9358d64ea6a91ed24c196f3add29a1f958c6416 /tcg/tcg-op-gvec.h | |
| parent | 532ba368a13712724137228b5e7e9435994d25e1 (diff) | |
| download | qemu-38dc12947ec9106237f9cdbd428792c985cd86ae.zip qemu-38dc12947ec9106237f9cdbd428792c985cd86ae.tar.gz qemu-38dc12947ec9106237f9cdbd428792c985cd86ae.tar.bz2 | |
tcg: Add support for vector bitwise select
This operation performs d = (b & a) | (c & ~a), and is present
on a majority of host vector units. Include gvec expanders.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg-op-gvec.h')
| -rw-r--r-- | tcg/tcg-op-gvec.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tcg/tcg-op-gvec.h b/tcg/tcg-op-gvec.h index 52a398c..2a9e0c7 100644 --- a/tcg/tcg-op-gvec.h +++ b/tcg/tcg-op-gvec.h @@ -343,6 +343,13 @@ void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, uint32_t oprsz, uint32_t maxsz); /* + * Perform vector bit select: d = (b & a) | (c & ~a). + */ +void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz); + +/* * 64-bit vector operations. Use these when the register has been allocated * with tcg_global_mem_new_i64, and so we cannot also address it via pointer. * OPRSZ = MAXSZ = 8. |