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| author | Richard Henderson <rth@twiddle.net> | 2010-02-16 14:23:39 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-02-20 08:34:42 +0000 |
| commit | 18c8f7a35d7b771392326c5723abe4e6b5908ca0 (patch) | |
| tree | bd4a771a3b3bb74177c45917f5591a5b1f1d8f61 /tcg/sparc | |
| parent | dc69960dd6d5387932889fe1ef0c2cead324ae82 (diff) | |
| download | qemu-18c8f7a35d7b771392326c5723abe4e6b5908ca0.zip qemu-18c8f7a35d7b771392326c5723abe4e6b5908ca0.tar.gz qemu-18c8f7a35d7b771392326c5723abe4e6b5908ca0.tar.bz2 | |
tcg-sparc: Implement ORC.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/sparc')
| -rw-r--r-- | tcg/sparc/tcg-target.c | 5 | ||||
| -rw-r--r-- | tcg/sparc/tcg-target.h | 2 |
2 files changed, 7 insertions, 0 deletions
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 1ea474d..891b8c4 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1223,6 +1223,9 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, OP_32_64(or): c = ARITH_OR; goto gen_arith; + OP_32_64(orc): + c = ARITH_ORN; + goto gen_arith; OP_32_64(xor): c = ARITH_XOR; goto gen_arith; @@ -1442,6 +1445,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_and_i32, { "r", "r", "rJ" } }, { INDEX_op_andc_i32, { "r", "r", "rJ" } }, { INDEX_op_or_i32, { "r", "r", "rJ" } }, + { INDEX_op_orc_i32, { "r", "r", "rJ" } }, { INDEX_op_xor_i32, { "r", "r", "rJ" } }, { INDEX_op_shl_i32, { "r", "r", "rJ" } }, @@ -1500,6 +1504,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_and_i64, { "r", "r", "rJ" } }, { INDEX_op_andc_i64, { "r", "r", "rJ" } }, { INDEX_op_or_i64, { "r", "r", "rJ" } }, + { INDEX_op_orc_i64, { "r", "r", "rJ" } }, { INDEX_op_xor_i64, { "r", "r", "rJ" } }, { INDEX_op_shl_i64, { "r", "r", "rJ" } }, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 4ea0c19..dc68787 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -94,6 +94,7 @@ enum { #define TCG_TARGET_HAS_neg_i32 #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_andc_i32 +#define TCG_TARGET_HAS_orc_i32 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_ext32s_i64 @@ -101,6 +102,7 @@ enum { #define TCG_TARGET_HAS_neg_i64 #define TCG_TARGET_HAS_not_i64 #define TCG_TARGET_HAS_andc_i64 +#define TCG_TARGET_HAS_orc_i64 #endif //#define TCG_TARGET_HAS_bswap32_i32 |