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| author | Richard Henderson <rth@twiddle.net> | 2013-02-19 23:51:51 -0800 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2013-02-23 17:25:28 +0000 |
| commit | 803d805bcef4ea7b7d6ef0b4929263e1160d6b3c (patch) | |
| tree | 00ad40615516cd881536b063c7452f854d863459 /tcg/sparc/tcg-target.c | |
| parent | bbc863bfecfb3e3a3e21ce569e25046e24c0487c (diff) | |
| download | qemu-803d805bcef4ea7b7d6ef0b4929263e1160d6b3c.zip qemu-803d805bcef4ea7b7d6ef0b4929263e1160d6b3c.tar.gz qemu-803d805bcef4ea7b7d6ef0b4929263e1160d6b3c.tar.bz2 | |
tcg-sparc: Always implement 32-bit multiword ops
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'tcg/sparc/tcg-target.c')
| -rw-r--r-- | tcg/sparc/tcg-target.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 03db514..6d489fc 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1327,6 +1327,8 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, args[3], const_args[3], args[4], const_args[4]); break; +#endif + case INDEX_op_add2_i32: tcg_out_addsub2(s, args[0], args[1], args[2], args[3], args[4], const_args[4], args[5], const_args[5], @@ -1342,7 +1344,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, ARITH_UMUL); tcg_out_rdy(s, args[1]); break; -#endif case INDEX_op_qemu_ld8u: tcg_out_qemu_ld(s, args, 0); @@ -1511,10 +1512,11 @@ static const TCGTargetOpDef sparc_op_defs[] = { #if TCG_TARGET_REG_BITS == 32 { INDEX_op_brcond2_i32, { "rZ", "rZ", "rJ", "rJ" } }, { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rJ", "rJ" } }, +#endif + { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } }, { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } }, -#endif #if TCG_TARGET_REG_BITS == 64 { INDEX_op_mov_i64, { "r", "r" } }, |