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| author | Keith Packard <keithp@keithp.com> | 2021-01-08 22:42:52 +0000 |
|---|---|---|
| committer | Alex Bennée <alex.bennee@linaro.org> | 2021-01-18 10:05:06 +0000 |
| commit | a10b9d93ecea0a8f01eb6de56274b1bcb101083b (patch) | |
| tree | 24d8b952a691501fa22791881425539e33535d5a /tcg/riscv/tcg-target.c.inc | |
| parent | 095f8c029319b79cce487e3b566cd826b93da3e6 (diff) | |
| download | qemu-a10b9d93ecea0a8f01eb6de56274b1bcb101083b.zip qemu-a10b9d93ecea0a8f01eb6de56274b1bcb101083b.tar.gz qemu-a10b9d93ecea0a8f01eb6de56274b1bcb101083b.tar.bz2 | |
riscv: Add semihosting support
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting version 0.2 as
documented in
https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2
Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20210107170717.2098982-6-keithp@keithp.com>
Message-Id: <20210108224256.2321-17-alex.bennee@linaro.org>
Diffstat (limited to 'tcg/riscv/tcg-target.c.inc')
0 files changed, 0 insertions, 0 deletions