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authorRichard Henderson <richard.henderson@linaro.org>2019-06-23 19:04:46 +0200
committerRichard Henderson <richard.henderson@linaro.org>2019-10-14 07:10:13 -0700
commit597cf978926ca3a745482a11096de8d433c6be1c (patch)
tree4ba088efd3dbd917f8e2808c1983103be61ae0df /tcg/ppc
parentd9897efa1fd3174eca5268ba017aa39242e5ddc5 (diff)
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tcg/ppc: Support vector dup2
This is only used for 32-bit hosts. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'tcg/ppc')
-rw-r--r--tcg/ppc/tcg-target.inc.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index d4b3354..8a50813 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -3102,6 +3102,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_dup2_vec:
+ assert(TCG_TARGET_REG_BITS == 32);
+ /* With inputs a1 = xLxx, a2 = xHxx */
+ tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
+ tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
+ tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
+ return;
+
case INDEX_op_ppc_mrgh_vec:
insn = mrgh_op[vece];
break;
@@ -3480,6 +3488,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_ppc_mulou_vec:
case INDEX_op_ppc_pkum_vec:
case INDEX_op_ppc_rotl_vec:
+ case INDEX_op_dup2_vec:
return &v_v_v;
case INDEX_op_not_vec:
case INDEX_op_dup_vec: