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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-03-22 13:52:09 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-06-10 07:03:34 -0700 |
| commit | a40ec84ee2b02086e27fab78a152c20b09c723cf (patch) | |
| tree | cf5efed68e90ae2240ecf558eddb0e18d890e275 /tcg/ppc | |
| parent | 74433bf083b0766aba81534f92de13194f23ff3e (diff) | |
| download | qemu-a40ec84ee2b02086e27fab78a152c20b09c723cf.zip qemu-a40ec84ee2b02086e27fab78a152c20b09c723cf.tar.gz qemu-a40ec84ee2b02086e27fab78a152c20b09c723cf.tar.bz2 | |
tcg: Create struct CPUTLB
Move all softmmu tlb data into this structure. Arrange the
members so that we are able to place mask+table together and
at a smaller absolute offset from ENV.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/ppc')
| -rw-r--r-- | tcg/ppc/tcg-target.inc.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c index 30c095d..d69c18a 100644 --- a/tcg/ppc/tcg-target.inc.c +++ b/tcg/ppc/tcg-target.inc.c @@ -1498,10 +1498,6 @@ static void * const qemu_st_helpers[16] = { [MO_BEQ] = helper_be_stq_mmu, }; -/* We expect tlb_mask to be before tlb_table. */ -QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table) < - offsetof(CPUArchState, tlb_mask)); - /* Perform the TLB load and compare. Places the result of the comparison in CR7, loads the addend of the TLB into R3, and returns the register containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ @@ -1514,8 +1510,8 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc, = (is_read ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); - int mask_off = offsetof(CPUArchState, tlb_mask[mem_index]); - int table_off = offsetof(CPUArchState, tlb_table[mem_index]); + int mask_off = offsetof(CPUArchState, tlb_.f[mem_index].mask); + int table_off = offsetof(CPUArchState, tlb_.f[mem_index].table); TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; unsigned s_bits = opc & MO_SIZE; unsigned a_bits = get_alignment_bits(opc); |