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| author | Richard Henderson <richard.henderson@linaro.org> | 2019-09-30 03:39:24 +0000 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-10-14 07:10:25 -0700 |
| commit | 64ff1c6d21745f2be89c76604391ae454f8490d0 (patch) | |
| tree | 063060a5a26333c9c2c2fb7a7268e6a03e217e82 /tcg/ppc/tcg-target.h | |
| parent | 47c906ae6f54fa10b3f072863d8993e790a14439 (diff) | |
| download | qemu-64ff1c6d21745f2be89c76604391ae454f8490d0.zip qemu-64ff1c6d21745f2be89c76604391ae454f8490d0.tar.gz qemu-64ff1c6d21745f2be89c76604391ae454f8490d0.tar.bz2 | |
tcg/ppc: Update vector support for v2.07 Altivec
These new instructions are conditional only on MSR.VEC and
are thus part of the Altivec instruction set, and not VSX.
This includes lots of double-word arithmetic and a few extra
logical operations.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/ppc/tcg-target.h')
| -rw-r--r-- | tcg/ppc/tcg-target.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index c974ca2..13197ed 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -61,6 +61,7 @@ typedef enum { typedef enum { tcg_isa_base, tcg_isa_2_06, + tcg_isa_2_07, tcg_isa_3_00, } TCGPowerISA; @@ -69,6 +70,7 @@ extern bool have_altivec; extern bool have_vsx; #define have_isa_2_06 (have_isa >= tcg_isa_2_06) +#define have_isa_2_07 (have_isa >= tcg_isa_2_07) #define have_isa_3_00 (have_isa >= tcg_isa_3_00) /* optional instructions automatically implemented */ @@ -155,7 +157,7 @@ extern bool have_vsx; #define TCG_TARGET_HAS_v256 0 #define TCG_TARGET_HAS_andc_vec 1 -#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_orc_vec have_isa_2_07 #define TCG_TARGET_HAS_not_vec 1 #define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_abs_vec 0 |