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author | Richard Henderson <richard.henderson@linaro.org> | 2023-04-05 14:49:59 -0700 |
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committer | Richard Henderson <richard.henderson@linaro.org> | 2023-04-23 08:21:19 +0100 |
commit | 753e42eada5c790bb3727c262f2e368e81cc788f (patch) | |
tree | 854969ea72b1ed34b29709139bafc6a4b9cc656d /tcg/mips | |
parent | d0e66c897f2cdfb0807b76567a17d7811487fac3 (diff) | |
download | qemu-753e42eada5c790bb3727c262f2e368e81cc788f.zip qemu-753e42eada5c790bb3727c262f2e368e81cc788f.tar.gz qemu-753e42eada5c790bb3727c262f2e368e81cc788f.tar.bz2 |
tcg: Split out tcg_out_ext16s
We will need a backend interface for performing 16-bit sign-extend.
Use it in tcg_reg_alloc_op in the meantime.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips')
-rw-r--r-- | tcg/mips/tcg-target.c.inc | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 5a712e3..9d305b9 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -563,6 +563,12 @@ static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); } +static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) +{ + tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); + tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); +} + static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, tcg_target_long imm) { @@ -2256,9 +2262,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_not_i64: i1 = OPC_NOR; goto do_unary; - case INDEX_op_ext16s_i32: - case INDEX_op_ext16s_i64: - i1 = OPC_SEH; do_unary: tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); break; @@ -2430,6 +2433,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_ext8s_i64: case INDEX_op_ext8u_i32: case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: default: g_assert_not_reached(); } |