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| author | Richard Henderson <rth@twiddle.net> | 2017-07-31 22:02:31 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-09-07 11:57:34 -0700 |
| commit | a85833933628384d74ec412024d55cf012640287 (patch) | |
| tree | cd3ed9260f5c9813102ffce4c006e7bbf3419c03 /tcg/mips | |
| parent | cda4a338c4243fa3bff4498b935340ac7121cc76 (diff) | |
| download | qemu-a85833933628384d74ec412024d55cf012640287.zip qemu-a85833933628384d74ec412024d55cf012640287.tar.gz qemu-a85833933628384d74ec412024d55cf012640287.tar.bz2 | |
tcg: Move USE_DIRECT_JUMP discriminator to tcg/cpu/tcg-target.h
Replace the USE_DIRECT_JUMP ifdef with a TCG_TARGET_HAS_direct_jump
boolean test. Replace the tb_set_jmp_target1 ifdef with an unconditional
function tb_target_set_jmp_target.
While we're touching all backends, add a parameter for tb->tc_ptr;
we're going to need it shortly for some backends.
Move tb_set_jmp_target and tb_add_jump from exec-all.h to cpu-exec.c.
This opens the possibility for TCG_TARGET_HAS_direct_jump to be
a runtime decision -- based on host cpu capabilities, the size of
code_gen_buffer, or a future debugging switch.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.h | 5 | ||||
| -rw-r--r-- | tcg/mips/tcg-target.inc.c | 3 |
2 files changed, 6 insertions, 2 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e9558d1..928a762 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -131,6 +131,7 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_mulsh_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_direct_jump 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 @@ -201,11 +202,13 @@ extern bool use_mips32r2_instructions; #include <sys/cachectl.h> #endif +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { cacheflush ((void *)start, stop-start, ICACHE); } -#define TCG_TARGET_DEFAULT_MO (0) +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #endif diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index 1a8169f..04f8c83 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -2642,7 +2642,8 @@ static void tcg_target_init(TCGContext *s) tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ } -void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) { atomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); flush_icache_range(jmp_addr, jmp_addr + 4); |