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| author | Brad <brad@comstyle.com> | 2011-05-25 23:06:00 -0400 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-06-03 18:23:53 +0200 |
| commit | 03938c133e60c10a6903ddf71021d76496d69cb0 (patch) | |
| tree | ccace830090249f6bf6fca9b5f0a058d434ea881 /tcg/mips | |
| parent | b7fa9214d8d4f57992c9acd0ccb125c54a095f00 (diff) | |
| download | qemu-03938c133e60c10a6903ddf71021d76496d69cb0.zip qemu-03938c133e60c10a6903ddf71021d76496d69cb0.tar.gz qemu-03938c133e60c10a6903ddf71021d76496d69cb0.tar.bz2 | |
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD.
Use the correct header in the TCG MIPS code to find cacheflush() on OpenBSD
to fix compilation of the MIPS host support for OpenBSD/mips64 based architecures.
Signed-off-by: Brad Smith <brad@comstyle.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 0028bfa..8cb7d88 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -102,7 +102,11 @@ enum { /* guest base is supported */ #define TCG_TARGET_HAS_GUEST_BASE +#ifdef __OpenBSD__ +#include <machine/sysarch.h> +#else #include <sys/cachectl.h> +#endif static inline void flush_icache_range(unsigned long start, unsigned long stop) { |