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| author | Kele Huang <kele.hwang@gmail.com> | 2021-04-01 18:04:57 +0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-04-05 07:32:56 -0700 |
| commit | 4e655e3cd80535328794c763681a6aa11a69178f (patch) | |
| tree | a967ecb592a392dee850eb0f473ec3a9fa7a3bf6 /tcg/mips | |
| parent | 25d75c99b2e5941c67049ee776efdb226414f4c6 (diff) | |
| download | qemu-4e655e3cd80535328794c763681a6aa11a69178f.zip qemu-4e655e3cd80535328794c763681a6aa11a69178f.tar.gz qemu-4e655e3cd80535328794c763681a6aa11a69178f.tar.bz2 | |
tcg/mips: Fix SoftTLB comparison on mips backend
The addrl used to compare with SoftTLB entry should be sign-extended
in common case, and it will cause constant failing in SoftTLB
comparisons for the addrl whose address is over 0x80000000 on the
emulation of 32-bit guest on 64-bit host.
This is an important performance bug fix. Spec2000 gzip rate increase
from ~45 to ~140 on Loongson 3A4000 (MIPS compatible platform).
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210401100457.191458-1-kele.hwang@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.c.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 8738a3a..8b16726 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1201,13 +1201,13 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); } - tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); /* Zero extend a 32-bit guest address for a 64-bit host. */ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { tcg_out_ext32u(s, base, addrl); addrl = base; } + tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); label_ptr[0] = s->code_ptr; tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); |