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| author | Aurelien Jarno <aurelien@aurel32.net> | 2015-07-30 22:11:51 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2015-08-01 09:39:33 +0200 |
| commit | 4214a8cb7c15ec43d4b2a43ebf248b273a0f4d45 (patch) | |
| tree | e17cfc8bdacb7d190477578bf9f4a61349f3f1ce /tcg/mips | |
| parent | e72c4fb81db52be881c9356f1c60e0a7817d2d32 (diff) | |
| download | qemu-4214a8cb7c15ec43d4b2a43ebf248b273a0f4d45.zip qemu-4214a8cb7c15ec43d4b2a43ebf248b273a0f4d45.tar.gz qemu-4214a8cb7c15ec43d4b2a43ebf248b273a0f4d45.tar.bz2 | |
tcg/mips: Mask TCGMemOp appropriately for indexing
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG MIPS backend.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 8dce19c..064db46 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1105,7 +1105,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, TCGMemOp opc) { - switch (opc) { + switch (opc & (MO_SSIZE | MO_BSWAP)) { case MO_UB: tcg_out_opc_imm(s, OPC_LBU, datalo, base, 0); break; @@ -1195,7 +1195,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, TCGReg base, TCGMemOp opc) { - switch (opc) { + switch (opc & (MO_SIZE | MO_BSWAP)) { case MO_8: tcg_out_opc_imm(s, OPC_SB, datalo, base, 0); break; |