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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-12-14 08:02:33 -0600 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-01-02 21:03:36 +0100 |
| commit | 084cfca143487d9b3ef37e7ee117f30e8e301af1 (patch) | |
| tree | 9aa2651b668bdd7421d58814608e8b7bb20af5f5 /tcg/mips | |
| parent | 3b9bd3f46b3b92501186acd18e81d3e8510b7b09 (diff) | |
| download | qemu-084cfca143487d9b3ef37e7ee117f30e8e301af1.zip qemu-084cfca143487d9b3ef37e7ee117f30e8e301af1.tar.gz qemu-084cfca143487d9b3ef37e7ee117f30e8e301af1.tar.bz2 | |
util: Extract flush_icache_range to cacheflush.c
This has been a tcg-specific function, but is also in use
by hardware accelerators via physmem.c. This can cause
link errors when tcg is disabled.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Joelle van Dyne <j@getutm.app>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214140314.18544-3-richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'tcg/mips')
| -rw-r--r-- | tcg/mips/tcg-target.h | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index c6b091d..92c1d63 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -198,20 +198,9 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ #endif -#ifdef __OpenBSD__ -#include <machine/sysarch.h> -#else -#include <sys/cachectl.h> -#endif - #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 -static inline void flush_icache_range(uintptr_t start, uintptr_t stop) -{ - cacheflush ((void *)start, stop-start, ICACHE); -} - void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU |