diff options
| author | Jin Guojie <jinguojie@loongson.cn> | 2017-01-05 12:57:46 +0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-06 10:03:54 -0800 |
| commit | bb08afe9f0aee1a3f5c23508e2511b882ca31e1b (patch) | |
| tree | 351a7eb593bfc57e2c88ef4bcf1865c4fedf2df4 /tcg/mips/tcg-target.h | |
| parent | ffe22bf51065dd33022cf91f77a821d1f11c250d (diff) | |
| download | qemu-bb08afe9f0aee1a3f5c23508e2511b882ca31e1b.zip qemu-bb08afe9f0aee1a3f5c23508e2511b882ca31e1b.tar.gz qemu-bb08afe9f0aee1a3f5c23508e2511b882ca31e1b.tar.bz2 | |
tcg-mips: Move bswap code to a subroutine
Without the mips32r2 instructions to perform swapping, bswap is quite large,
dominating the size of each reverse-endian qemu_ld/qemu_st operation.
Create a subroutine in the prologue block. The subroutine requires extra
reserved registers (TCG_TMP[2, 3]). Using these within qemu_ld means that
we need not place additional restrictions on the qemu_ld outputs.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: James Hogan <james.hogan@imgtec.com>
Tested-by: YunQiang Su <wzssyqa@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Jin Guojie <jinguojie@loongson.cn>
Message-Id: <1483592275-4496-2-git-send-email-jinguojie@loongson.cn>
Diffstat (limited to 'tcg/mips/tcg-target.h')
| -rw-r--r-- | tcg/mips/tcg-target.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 3aeac87..a6871fb 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -117,11 +117,11 @@ extern bool use_mips32r2_instructions; #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) #define TCG_TARGET_HAS_muluh_i32 1 #define TCG_TARGET_HAS_mulsh_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 /* optional instructions detected at runtime */ #define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions -#define TCG_TARGET_HAS_bswap32_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions |