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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-09-03 15:56:24 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-10-08 05:57:32 -0500 |
| commit | 74a117906b87ff9220e4baae5a7431d6f4eadd45 (patch) | |
| tree | d99fbe2a152523b0dd5b73fbd22e46aa2bdfd7cf /tcg/i386 | |
| parent | 66792f90f14fef18b25a168922877a367ecdca05 (diff) | |
| download | qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.zip qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.gz qemu-74a117906b87ff9220e4baae5a7431d6f4eadd45.tar.bz2 | |
tcg: Remove TCG_CT_REG
This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/i386')
| -rw-r--r-- | tcg/i386/tcg-target.c.inc | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 8661ec3..2f69607 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, { switch(*ct_str++) { case 'a': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EAX); break; case 'b': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EBX); break; case 'c': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ECX); break; case 'd': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDX); break; case 'S': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_ESI); break; case 'D': - ct->ct |= TCG_CT_REG; tcg_regset_set_reg(ct->regs, TCG_REG_EDI); break; case 'q': /* A register that can be used as a byte operand. */ - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; break; case 'Q': /* A register with an addressable second byte (e.g. %ah). */ - ct->ct |= TCG_CT_REG; ct->regs = 0xf; break; case 'r': /* A general register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_GENERAL_REGS; break; case 'W': @@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgConstraint *ct, break; case 'x': /* A vector register. */ - ct->ct |= TCG_CT_REG; ct->regs |= ALL_VECTOR_REGS; break; /* qemu_ld/st address constraint */ case 'L': - ct->ct |= TCG_CT_REG; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; tcg_regset_reset_reg(ct->regs, TCG_REG_L0); tcg_regset_reset_reg(ct->regs, TCG_REG_L1); |