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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-03-16 17:25:33 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-16 17:25:33 +0000 |
| commit | 2bb39a657abeac3f33ab3298177fb27c35f5b50a (patch) | |
| tree | 7321cd9130142ec3be88b69ffed917612f87ea98 /tcg/i386/tcg-target.inc.c | |
| parent | 9cc7d0cf6a6dc300db4db25421eff782623d6b18 (diff) | |
| parent | adb196cbd5cff26547bc32a208074f03f4c4a627 (diff) | |
| download | qemu-2bb39a657abeac3f33ab3298177fb27c35f5b50a.zip qemu-2bb39a657abeac3f33ab3298177fb27c35f5b50a.tar.gz qemu-2bb39a657abeac3f33ab3298177fb27c35f5b50a.tar.bz2 | |
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180316' into staging
Queued TCG patches
# gpg: Signature made Thu 15 Mar 2018 17:17:31 GMT
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-tcg-20180316:
tcg: Add choose_vector_size
tcg/i386: Support INDEX_op_dup2_vec for -m32
tcg: Improve tcg_gen_muli_i32/i64
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg/i386/tcg-target.inc.c')
| -rw-r--r-- | tcg/i386/tcg-target.inc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fc05909..d7e59e7 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, case INDEX_op_x86_packus_vec: insn = packus_insn[vece]; goto gen_simd; +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: + /* Constraints have already placed both 32-bit inputs in xmm regs. */ + insn = OPC_PUNPCKLDQ; + goto gen_simd; +#endif gen_simd: tcg_debug_assert(insn != OPC_UD2); if (type == TCG_TYPE_V256) { @@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_x86_vperm2i128_vec: case INDEX_op_x86_punpckl_vec: case INDEX_op_x86_punpckh_vec: +#if TCG_TARGET_REG_BITS == 32 + case INDEX_op_dup2_vec: +#endif return &x_x_x; case INDEX_op_dup_vec: case INDEX_op_shli_vec: |