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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-05-03 16:47:52 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-06-04 11:50:11 -0700 |
| commit | 000cf4777aadda69d14a6994ca0d195a36733cbd (patch) | |
| tree | a01d2bbc4dbf2ac318f9754d18b2ae05d8c14a2f /tcg/arm/tcg-target.h | |
| parent | a4fbbd779a29b912299bc2830f0157513080ddb7 (diff) | |
| download | qemu-000cf4777aadda69d14a6994ca0d195a36733cbd.zip qemu-000cf4777aadda69d14a6994ca0d195a36733cbd.tar.gz qemu-000cf4777aadda69d14a6994ca0d195a36733cbd.tar.bz2 | |
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/arm/tcg-target.h')
| -rw-r--r-- | tcg/arm/tcg-target.h | 48 |
1 files changed, 42 insertions, 6 deletions
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 8d1fee6..a9dc09b 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -78,19 +78,38 @@ typedef enum { TCG_REG_R13, TCG_REG_R14, TCG_REG_PC, + + TCG_REG_Q0, + TCG_REG_Q1, + TCG_REG_Q2, + TCG_REG_Q3, + TCG_REG_Q4, + TCG_REG_Q5, + TCG_REG_Q6, + TCG_REG_Q7, + TCG_REG_Q8, + TCG_REG_Q9, + TCG_REG_Q10, + TCG_REG_Q11, + TCG_REG_Q12, + TCG_REG_Q13, + TCG_REG_Q14, + TCG_REG_Q15, + + TCG_AREG0 = TCG_REG_R6, + TCG_REG_CALL_STACK = TCG_REG_R13, } TCGReg; -#define TCG_TARGET_NB_REGS 16 +#define TCG_TARGET_NB_REGS 32 #ifdef __ARM_ARCH_EXT_IDIV__ #define use_idiv_instructions 1 #else extern bool use_idiv_instructions; #endif - +#define use_neon_instructions 0 /* used for function call generation */ -#define TCG_REG_CALL_STACK TCG_REG_R13 #define TCG_TARGET_STACK_ALIGN 8 #define TCG_TARGET_CALL_ALIGN_ARGS 1 #define TCG_TARGET_CALL_STACK_OFFSET 0 @@ -128,9 +147,26 @@ extern bool use_idiv_instructions; #define TCG_TARGET_HAS_direct_jump 0 #define TCG_TARGET_HAS_qemu_st8_i32 0 -enum { - TCG_AREG0 = TCG_REG_R6, -}; +#define TCG_TARGET_HAS_v64 use_neon_instructions +#define TCG_TARGET_HAS_v128 use_neon_instructions +#define TCG_TARGET_HAS_v256 0 + +#define TCG_TARGET_HAS_andc_vec 0 +#define TCG_TARGET_HAS_orc_vec 0 +#define TCG_TARGET_HAS_not_vec 0 +#define TCG_TARGET_HAS_neg_vec 0 +#define TCG_TARGET_HAS_abs_vec 0 +#define TCG_TARGET_HAS_roti_vec 0 +#define TCG_TARGET_HAS_rots_vec 0 +#define TCG_TARGET_HAS_rotv_vec 0 +#define TCG_TARGET_HAS_shi_vec 0 +#define TCG_TARGET_HAS_shs_vec 0 +#define TCG_TARGET_HAS_shv_vec 0 +#define TCG_TARGET_HAS_mul_vec 0 +#define TCG_TARGET_HAS_sat_vec 0 +#define TCG_TARGET_HAS_minmax_vec 0 +#define TCG_TARGET_HAS_bitsel_vec 0 +#define TCG_TARGET_HAS_cmpsel_vec 0 #define TCG_TARGET_DEFAULT_MO (0) #define TCG_TARGET_HAS_MEMORY_BSWAP 1 |