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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-10-25 16:58:45 +0100 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-11-11 15:11:21 +0100 |
| commit | 97105f2921ee0a66d03ec5623150740602e80509 (patch) | |
| tree | 00c54d92e1ddf3b638f337243441c647989462ab /tcg/aarch64 | |
| parent | 654efcb511d394c1d3f5292c28503d1d19e5b1d3 (diff) | |
| download | qemu-97105f2921ee0a66d03ec5623150740602e80509.zip qemu-97105f2921ee0a66d03ec5623150740602e80509.tar.gz qemu-97105f2921ee0a66d03ec5623150740602e80509.tar.bz2 | |
tcg/aarch64/tcg-target.opc.h: Add copyright/license
Add the copyright/license boilerplate for target/aarch64/tcg-target.opc.h.
This file has only had two commits: 14e4c1e2355473ccb29
and 79525dfd08262d8, both by the same Linaro engineer.
The license is GPL-2-or-later, since that's what the
rest of tcg/aarch64 uses.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20191025155848.17362-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/aarch64')
| -rw-r--r-- | tcg/aarch64/tcg-target.opc.h | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/tcg/aarch64/tcg-target.opc.h b/tcg/aarch64/tcg-target.opc.h index 59e1d3f..26bfd9c 100644 --- a/tcg/aarch64/tcg-target.opc.h +++ b/tcg/aarch64/tcg-target.opc.h @@ -1,5 +1,14 @@ -/* Target-specific opcodes for host vector expansion. These will be - emitted by tcg_expand_vec_op. For those familiar with GCC internals, - consider these to be UNSPEC with names. */ +/* + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * (at your option) any later version. + * + * See the COPYING file in the top-level directory for details. + * + * Target-specific opcodes for host vector expansion. These will be + * emitted by tcg_expand_vec_op. For those familiar with GCC internals, + * consider these to be UNSPEC with names. + */ DEF(aa64_sshl_vec, 1, 2, 0, IMPLVEC) |