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| author | Richard Henderson <richard.henderson@linaro.org> | 2018-12-17 18:01:47 -0800 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-01-28 07:03:34 -0800 |
| commit | 8afaf0506606f8003ef696df849c5a98637a7a83 (patch) | |
| tree | 89779034a934a38716364a0a8d04e8ab66c584c0 /tcg/README | |
| parent | 5d6acdd4a485f15b1081acc523b99c1f1a7c42ab (diff) | |
| download | qemu-8afaf0506606f8003ef696df849c5a98637a7a83.zip qemu-8afaf0506606f8003ef696df849c5a98637a7a83.tar.gz qemu-8afaf0506606f8003ef696df849c5a98637a7a83.tar.bz2 | |
tcg: Add opcodes for vector saturated arithmetic
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/README')
| -rw-r--r-- | tcg/README | 9 |
1 files changed, 9 insertions, 0 deletions
@@ -554,6 +554,15 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32. Similarly, v0 = -v1. +* ssadd_vec: +* sssub_vec: +* usadd_vec: +* ussub_vec: + + Signed and unsigned saturating addition and subtraction. If the true + result is not representable within the element type, the element is + set to the minimum or maximum value for the type. + * and_vec v0, v1, v2 * or_vec v0, v1, v2 * xor_vec v0, v1, v2 |