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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-12-09 13:58:39 -0600 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2021-01-07 05:09:06 -1000 |
| commit | 07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1 (patch) | |
| tree | a22f2b213b2cb96c8e0e30c69bca9edb00b678bc /tcg/README | |
| parent | d2ef1b83a7a2047e0e36d7b62b3a5d151ab958f5 (diff) | |
| download | qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.zip qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.gz qemu-07ce0b05300de5bc8f1932a4cfbe38f3323e5ab1.tar.bz2 | |
tcg: Introduce INDEX_op_qemu_st8_i32
Enable this on i386 to restrict the set of input registers
for an 8-bit store, as required by the architecture. This
removes the last use of scratch registers for user-only mode.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/README')
| -rw-r--r-- | tcg/README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -502,6 +502,7 @@ goto_ptr opcode, emitting this op is equivalent to emitting exit_tb(0). * qemu_ld_i32/i64 t0, t1, flags, memidx * qemu_st_i32/i64 t0, t1, flags, memidx +* qemu_st8_i32 t0, t1, flags, memidx Load data at the guest address t1 into t0, or store data in t0 at guest address t1. The _i32/_i64 size applies to the size of the input/output @@ -518,6 +519,10 @@ of the memory access. For a 32-bit host, qemu_ld/st_i64 is guaranteed to only be used with a 64-bit memory access specified in flags. +For i386, qemu_st8_i32 is exactly like qemu_st_i32, except the size of +the memory operation is known to be 8-bit. This allows the backend to +provide a different set of register constraints. + ********* Host vector operations All of the vector ops have two parameters, TCGOP_VECL & TCGOP_VECE. |