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| author | Joe Komlodi <joe.komlodi@xilinx.com> | 2020-05-13 11:08:46 -0700 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2020-05-14 16:01:00 +0200 |
| commit | a44e82db0c0bada34af613029cf976f8bb7859d9 (patch) | |
| tree | e44793b0707362e9ffffcb8f3a530dc858892053 /target | |
| parent | 2016a6a765ad5283609183a5aa14d14285aaca6e (diff) | |
| download | qemu-a44e82db0c0bada34af613029cf976f8bb7859d9.zip qemu-a44e82db0c0bada34af613029cf976f8bb7859d9.tar.gz qemu-a44e82db0c0bada34af613029cf976f8bb7859d9.tar.bz2 | |
target/microblaze: gdb: Extend the number of registers presented to GDB
Increase the number of Microblaze registers QEMU will report when
talking to GDB.
Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <1589393329-223076-2-git-send-email-komlodi@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/microblaze/cpu.c | 2 | ||||
| -rw-r--r-- | target/microblaze/gdbstub.c | 52 |
2 files changed, 50 insertions, 4 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aa99830..51e5c85 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -329,7 +329,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) #endif dc->vmsd = &vmstate_mb_cpu; device_class_set_props(dc, mb_properties); - cc->gdb_num_core_regs = 32 + 5; + cc->gdb_num_core_regs = 32 + 27; cc->disas_set_info = mb_disas_set_info; cc->tcg_initialize = mb_tcg_init; diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index f41ebf1..54cc785 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -26,12 +26,37 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); CPUMBState *env = &cpu->env; + /* + * GDB expects registers to be reported in this order: + * R0-R31 + * PC-BTR + * PVR0-PVR11 + * EDR-TLBHI + * SLR-SHR + */ if (n < 32) { return gdb_get_reg32(mem_buf, env->regs[n]); } else { - return gdb_get_reg32(mem_buf, env->sregs[n - 32]); + n -= 32; + switch (n) { + case 0 ... 5: + return gdb_get_reg32(mem_buf, env->sregs[n]); + /* PVR12 is intentionally skipped */ + case 6 ... 17: + n -= 6; + return gdb_get_reg32(mem_buf, env->pvr.regs[n]); + case 18 ... 24: + /* Add an offset of 6 to resume where we left off with SRegs */ + n = n - 18 + 6; + return gdb_get_reg32(mem_buf, env->sregs[n]); + case 25: + return gdb_get_reg32(mem_buf, env->slr); + case 26: + return gdb_get_reg32(mem_buf, env->shr); + default: + return 0; + } } - return 0; } int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) @@ -50,7 +75,28 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) if (n < 32) { env->regs[n] = tmp; } else { - env->sregs[n - 32] = tmp; + n -= 32; + switch (n) { + case 0 ... 5: + env->sregs[n] = tmp; + break; + /* PVR12 is intentionally skipped */ + case 6 ... 17: + n -= 6; + env->pvr.regs[n] = tmp; + break; + case 18 ... 24: + /* Add an offset of 6 to resume where we left off with SRegs */ + n = n - 18 + 6; + env->sregs[n] = tmp; + break; + case 25: + env->slr = tmp; + break; + case 26: + env->shr = tmp; + break; + } } return 4; } |