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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-03-01 11:59:42 -1000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-03-02 19:27:36 +0000 |
| commit | 691f1ffdfc446acc1a9f0831fcced5012f6de52a (patch) | |
| tree | 1d98c944a11d9648075631a468481f83cce6805e /target | |
| parent | d5e51efb9f1842d85f24fb0e2fe298641de6e129 (diff) | |
| download | qemu-691f1ffdfc446acc1a9f0831fcced5012f6de52a.zip qemu-691f1ffdfc446acc1a9f0831fcced5012f6de52a.tar.gz qemu-691f1ffdfc446acc1a9f0831fcced5012f6de52a.tar.bz2 | |
target/arm: Set TCR_EL1.TSZ for user-only
Set this as the kernel would, to 48 bits, to keep the computation
of the address space correct for PAuth.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220301215958.157011-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dd64d17..7091684 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -206,10 +206,11 @@ static void arm_cpu_reset(DeviceState *dev) aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1); } /* + * Enable 48-bit address space (TODO: take reserved_va into account). * Enable TBI0 but not TBI1. * Note that this must match useronly_clean_ptr. */ - env->cp15.tcr_el[1].raw_tcr = (1ULL << 37); + env->cp15.tcr_el[1].raw_tcr = 5 | (1ULL << 37); /* Enable MTE */ if (cpu_isar_feature(aa64_mte, cpu)) { |