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authorNicholas Piggin <npiggin@gmail.com>2023-11-13 22:23:06 +1000
committerNicholas Piggin <npiggin@gmail.com>2024-02-23 23:24:43 +1000
commit1b72973d39b601b3766d157d3d9bf99033c35e7f (patch)
treeef00a1af5d29dcd787d476f98bddbe6dd884dbdf /target
parent2ab03484819d529184927314f3b541d7c2221b4a (diff)
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target/ppc: 440 optimise tlbwe TLB flushing
Have 440 tlbwe flush only the range corresponding to the addresses covered by the software TLB entry being modified rather than the entire TLB. This matches what 4xx does. Tested-by: BALATON Zoltan <balaton@eik.bme.hu> Acked-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'target')
-rw-r--r--target/ppc/mmu_helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 923779d..ba965f1 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -864,7 +864,7 @@ void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry,
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
- tlb_flush(env_cpu(env));
+ ppcemb_tlb_flush(env_cpu(env), tlb);
}
switch (word) {