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| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:59 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:59 +0100 |
| commit | 1702071302934af77a072b7ee7c5eadc45b37573 (patch) | |
| tree | 37f8ea2fe278ed251a409e0858a39574f78e4b72 /target | |
| parent | 8859ba3c9625e7ceb5599f457a344bcd7c5e112b (diff) | |
| download | qemu-1702071302934af77a072b7ee7c5eadc45b37573.zip qemu-1702071302934af77a072b7ee7c5eadc45b37573.tar.gz qemu-1702071302934af77a072b7ee7c5eadc45b37573.tar.bz2 | |
target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present
If the floating point extension is present, then the SG instruction
must clear the CONTROL_S.SFPA bit. Implement this.
(On a no-FPU system the bit will always be zero, so we don't need
to make the clearing of the bit conditional on ARM_FEATURE_VFP.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-8-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index c3d5fe0..45a9d92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8804,6 +8804,7 @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 ", executing it\n", env->regs[15]); env->regs[14] &= ~1; + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, true); xpsr_write(env, 0, XPSR_IT); env->regs[15] += 4; |