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authorHelge Deller <deller@gmx.de>2022-09-28 20:49:13 +0200
committerHelge Deller <deller@gmx.de>2022-12-19 23:13:59 +0100
commit0786a3b6051ed081ddaa8dfe1c1e13ce0cfabc4a (patch)
tree698a985291e93e110d060af2b1ac56511fa163b8 /target
parentc15dc499cc22f4a71639e42e36051e118761c25f (diff)
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target/hppa: Generate illegal instruction exception for 64-bit instructions
Qemu currently emulates a 32-bit CPU only, and crashes with this error when it faces a 64-bit load (e.g. "ldd 0(r26),r0") or a 64-bit store (e.g. "std r26,0(r26)") instruction in the guest: ERROR:../qemu/tcg/tcg-op.c:2822:tcg_canonicalize_memop: code should not be reached Add checks for 64-bit sizes and generate an illegal instruction exception if necessary. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/hppa/translate.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 1af7747..d15b9e2 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2899,14 +2899,22 @@ static bool trans_cmpiclr(DisasContext *ctx, arg_rri_cf *a)
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
- return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
+ if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ return gen_illegal(ctx);
+ } else {
+ return do_load(ctx, a->t, a->b, a->x, a->scale ? a->size : 0,
a->disp, a->sp, a->m, a->size | MO_TE);
+ }
}
static bool trans_st(DisasContext *ctx, arg_ldst *a)
{
assert(a->x == 0 && a->scale == 0);
- return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
+ if (unlikely(TARGET_REGISTER_BITS == 32 && a->size > MO_32)) {
+ return gen_illegal(ctx);
+ } else {
+ return do_store(ctx, a->t, a->b, a->disp, a->sp, a->m, a->size | MO_TE);
+ }
}
static bool trans_ldc(DisasContext *ctx, arg_ldst *a)