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| author | Peter Maydell <peter.maydell@linaro.org> | 2022-04-26 17:04:20 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-28 13:59:23 +0100 |
| commit | f81c60c24497e912d2fcf9d250c6f3de01db68b9 (patch) | |
| tree | 0cf8ccad8f2b04a91800987e6f4e43f3ef53b329 /target | |
| parent | 264a3b2eba3381980d17f23a7374edac691fd39a (diff) | |
| download | qemu-f81c60c24497e912d2fcf9d250c6f3de01db68b9.zip qemu-f81c60c24497e912d2fcf9d250c6f3de01db68b9.tar.gz qemu-f81c60c24497e912d2fcf9d250c6f3de01db68b9.tar.bz2 | |
target/arm: Advertise support for FEAT_TTL
The Arm FEAT_TTL architectural feature allows the guest to provide an
optional hint in an AArch64 TLB invalidate operation about which
translation table level holds the leaf entry for the address being
invalidated. QEMU's TLB implementation doesn't need that hint, and
we correctly ignore the (previously RES0) bits in TLB invalidate
operation values that are now used for the TTL field. So we can
simply advertise support for it in our 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb44c05..ec2d159 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -839,6 +839,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ cpu->isar.id_aa64mmfr2 = t; t = cpu->isar.id_aa64zfr0; |