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| author | Richard Henderson <richard.henderson@linaro.org> | 2022-04-26 09:30:22 -0700 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-28 13:38:15 +0100 |
| commit | dfbbf5e1f94341989f85f34c009df5ee7a511e30 (patch) | |
| tree | ab43b0f9f16df13fd62788182d1d08f3ea30cb38 /target | |
| parent | f5fd5f64b474b6765540f4ec894e89e4e8365096 (diff) | |
| download | qemu-dfbbf5e1f94341989f85f34c009df5ee7a511e30.zip qemu-dfbbf5e1f94341989f85f34c009df5ee7a511e30.tar.gz qemu-dfbbf5e1f94341989f85f34c009df5ee7a511e30.tar.bz2 | |
target/arm: Use tcg_constant for do_coproc_insn
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/translate.c | 43 |
1 files changed, 13 insertions, 30 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 9539d2e..e4f3db2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4689,8 +4689,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, * Note that on XScale all cp0..c13 registers do an access check * call in order to handle c15_cpar. */ - TCGv_ptr tmpptr; - TCGv_i32 tcg_syn, tcg_isread; uint32_t syndrome; /* Note that since we are an implementation which takes an @@ -4733,14 +4731,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - tmpptr = tcg_const_ptr(ri); - tcg_syn = tcg_const_i32(syndrome); - tcg_isread = tcg_const_i32(isread); - gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, - tcg_isread); - tcg_temp_free_ptr(tmpptr); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_isread); + gen_helper_access_check_cp_reg(cpu_env, + tcg_constant_ptr(ri), + tcg_constant_i32(syndrome), + tcg_constant_i32(isread)); } else if (ri->type & ARM_CP_RAISES_EXC) { /* * The readfn or writefn might raise an exception; @@ -4776,13 +4770,11 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, TCGv_i64 tmp64; TCGv_i32 tmp; if (ri->type & ARM_CP_CONST) { - tmp64 = tcg_const_i64(ri->resetvalue); + tmp64 = tcg_constant_i64(ri->resetvalue); } else if (ri->readfn) { - TCGv_ptr tmpptr; tmp64 = tcg_temp_new_i64(); - tmpptr = tcg_const_ptr(ri); - gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr); - tcg_temp_free_ptr(tmpptr); + gen_helper_get_cp_reg64(tmp64, cpu_env, + tcg_constant_ptr(ri)); } else { tmp64 = tcg_temp_new_i64(); tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); @@ -4797,13 +4789,10 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, } else { TCGv_i32 tmp; if (ri->type & ARM_CP_CONST) { - tmp = tcg_const_i32(ri->resetvalue); + tmp = tcg_constant_i32(ri->resetvalue); } else if (ri->readfn) { - TCGv_ptr tmpptr; tmp = tcg_temp_new_i32(); - tmpptr = tcg_const_ptr(ri); - gen_helper_get_cp_reg(tmp, cpu_env, tmpptr); - tcg_temp_free_ptr(tmpptr); + gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(ri)); } else { tmp = load_cpu_offset(ri->fieldoffset); } @@ -4833,24 +4822,18 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_temp_free_i32(tmplo); tcg_temp_free_i32(tmphi); if (ri->writefn) { - TCGv_ptr tmpptr = tcg_const_ptr(ri); - gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64); - tcg_temp_free_ptr(tmpptr); + gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), + tmp64); } else { tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); } tcg_temp_free_i64(tmp64); } else { + TCGv_i32 tmp = load_reg(s, rt); if (ri->writefn) { - TCGv_i32 tmp; - TCGv_ptr tmpptr; - tmp = load_reg(s, rt); - tmpptr = tcg_const_ptr(ri); - gen_helper_set_cp_reg(cpu_env, tmpptr, tmp); - tcg_temp_free_ptr(tmpptr); + gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), tmp); tcg_temp_free_i32(tmp); } else { - TCGv_i32 tmp = load_reg(s, rt); store_cpu_offset(tmp, ri->fieldoffset, 4); } } |