aboutsummaryrefslogtreecommitdiff
path: root/target
diff options
context:
space:
mode:
authorEduardo Habkost <ehabkost@redhat.com>2020-09-03 16:43:22 -0400
committerEduardo Habkost <ehabkost@redhat.com>2020-09-09 09:26:43 -0400
commitdb1015e92e04835c9eb50c29625fe566d1202dbd (patch)
tree41fbc0bf3e3f29b7ecb339224a049e3f2a7db8fa /target
parent1c8eef0227e2942264063f22f10a06b84e0d3fa9 (diff)
downloadqemu-db1015e92e04835c9eb50c29625fe566d1202dbd.zip
qemu-db1015e92e04835c9eb50c29625fe566d1202dbd.tar.gz
qemu-db1015e92e04835c9eb50c29625fe566d1202dbd.tar.bz2
Move QOM typedefs and add missing includes
Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=QOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=MoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com> Message-Id: <20200831210740.126168-10-ehabkost@redhat.com> Message-Id: <20200831210740.126168-11-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/alpha/cpu-qom.h8
-rw-r--r--target/arm/cpu-qom.h13
-rw-r--r--target/arm/idau.h5
-rw-r--r--target/avr/cpu-qom.h8
-rw-r--r--target/cris/cpu-qom.h8
-rw-r--r--target/hppa/cpu-qom.h8
-rw-r--r--target/i386/cpu-qom.h8
-rw-r--r--target/i386/sev.c3
-rw-r--r--target/lm32/cpu-qom.h8
-rw-r--r--target/m68k/cpu-qom.h8
-rw-r--r--target/microblaze/cpu-qom.h8
-rw-r--r--target/mips/cpu-qom.h8
-rw-r--r--target/moxie/cpu.h11
-rw-r--r--target/nios2/cpu.h11
-rw-r--r--target/openrisc/cpu.h11
-rw-r--r--target/ppc/cpu-qom.h8
-rw-r--r--target/ppc/cpu.h1
-rw-r--r--target/riscv/cpu.h11
-rw-r--r--target/rx/cpu-qom.h6
-rw-r--r--target/s390x/cpu-qom.h8
-rw-r--r--target/sh4/cpu-qom.h8
-rw-r--r--target/sparc/cpu-qom.h8
-rw-r--r--target/tilegx/cpu.h11
-rw-r--r--target/tricore/cpu-qom.h8
-rw-r--r--target/unicore32/cpu-qom.h8
-rw-r--r--target/xtensa/cpu-qom.h8
26 files changed, 133 insertions, 78 deletions
diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 08832fa..1124668 100644
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_ALPHA_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_ALPHA_CPU "alpha-cpu"
+typedef struct AlphaCPU AlphaCPU;
+typedef struct AlphaCPUClass AlphaCPUClass;
#define ALPHA_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(AlphaCPUClass, (klass), TYPE_ALPHA_CPU)
#define ALPHA_CPU(obj) \
@@ -38,15 +41,14 @@
*
* An Alpha CPU model.
*/
-typedef struct AlphaCPUClass {
+struct AlphaCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} AlphaCPUClass;
+};
-typedef struct AlphaCPU AlphaCPU;
#endif
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index fdef05c..d0c68b0 100644
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -21,11 +21,14 @@
#define QEMU_ARM_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
struct arm_boot_info;
#define TYPE_ARM_CPU "arm-cpu"
+typedef struct ARMCPU ARMCPU;
+typedef struct ARMCPUClass ARMCPUClass;
#define ARM_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
#define ARM_CPU(obj) \
@@ -51,7 +54,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
*
* An ARM CPU model.
*/
-typedef struct ARMCPUClass {
+struct ARMCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -59,21 +62,21 @@ typedef struct ARMCPUClass {
const ARMCPUInfo *info;
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} ARMCPUClass;
+};
-typedef struct ARMCPU ARMCPU;
#define TYPE_AARCH64_CPU "aarch64-cpu"
+typedef struct AArch64CPUClass AArch64CPUClass;
#define AARCH64_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
#define AARCH64_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AARCH64_CPU)
-typedef struct AArch64CPUClass {
+struct AArch64CPUClass {
/*< private >*/
ARMCPUClass parent_class;
/*< public >*/
-} AArch64CPUClass;
+};
void register_cp_regs_for_features(ARMCPU *cpu);
void init_cpreg_list(ARMCPU *cpu);
diff --git a/target/arm/idau.h b/target/arm/idau.h
index 7c0e4e3..2f09bbb 100644
--- a/target/arm/idau.h
+++ b/target/arm/idau.h
@@ -33,6 +33,7 @@
#define TYPE_IDAU_INTERFACE "idau-interface"
#define IDAU_INTERFACE(obj) \
INTERFACE_CHECK(IDAUInterface, (obj), TYPE_IDAU_INTERFACE)
+typedef struct IDAUInterfaceClass IDAUInterfaceClass;
#define IDAU_INTERFACE_CLASS(class) \
OBJECT_CLASS_CHECK(IDAUInterfaceClass, (class), TYPE_IDAU_INTERFACE)
#define IDAU_INTERFACE_GET_CLASS(obj) \
@@ -42,7 +43,7 @@ typedef struct IDAUInterface IDAUInterface;
#define IREGION_NOTVALID -1
-typedef struct IDAUInterfaceClass {
+struct IDAUInterfaceClass {
InterfaceClass parent;
/* Check the specified address and return the IDAU security information
@@ -54,6 +55,6 @@ typedef struct IDAUInterfaceClass {
*/
void (*check)(IDAUInterface *ii, uint32_t address, int *iregion,
bool *exempt, bool *ns, bool *nsc);
-} IDAUInterfaceClass;
+};
#endif
diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index d23ad43..fac8430 100644
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -22,9 +22,12 @@
#define QEMU_AVR_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_AVR_CPU "avr-cpu"
+typedef struct AVRCPU AVRCPU;
+typedef struct AVRCPUClass AVRCPUClass;
#define AVR_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(AVRCPUClass, (klass), TYPE_AVR_CPU)
#define AVR_CPU(obj) \
@@ -40,14 +43,13 @@
*
* A AVR CPU model.
*/
-typedef struct AVRCPUClass {
+struct AVRCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} AVRCPUClass;
+};
-typedef struct AVRCPU AVRCPU;
#endif /* !defined (QEMU_AVR_CPU_QOM_H) */
diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index f1de604..cac3e9a 100644
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_CRIS_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_CRIS_CPU "cris-cpu"
+typedef struct CRISCPU CRISCPU;
+typedef struct CRISCPUClass CRISCPUClass;
#define CRIS_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(CRISCPUClass, (klass), TYPE_CRIS_CPU)
#define CRIS_CPU(obj) \
@@ -39,7 +42,7 @@
*
* A CRIS CPU model.
*/
-typedef struct CRISCPUClass {
+struct CRISCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -48,8 +51,7 @@ typedef struct CRISCPUClass {
DeviceReset parent_reset;
uint32_t vr;
-} CRISCPUClass;
+};
-typedef struct CRISCPU CRISCPU;
#endif
diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index b1f6045..295b2aa 100644
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_HPPA_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_HPPA_CPU "hppa-cpu"
+typedef struct HPPACPU HPPACPU;
+typedef struct HPPACPUClass HPPACPUClass;
#define HPPA_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(HPPACPUClass, (klass), TYPE_HPPA_CPU)
#define HPPA_CPU(obj) \
@@ -38,15 +41,14 @@
*
* An HPPA CPU model.
*/
-typedef struct HPPACPUClass {
+struct HPPACPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} HPPACPUClass;
+};
-typedef struct HPPACPU HPPACPU;
#endif
diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 3e96f8d..6b0bf47 100644
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -22,6 +22,7 @@
#include "hw/core/cpu.h"
#include "qemu/notify.h"
+#include "qom/object.h"
#ifdef TARGET_X86_64
#define TYPE_X86_CPU "x86_64-cpu"
@@ -29,6 +30,8 @@
#define TYPE_X86_CPU "i386-cpu"
#endif
+typedef struct X86CPU X86CPU;
+typedef struct X86CPUClass X86CPUClass;
#define X86_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(X86CPUClass, (klass), TYPE_X86_CPU)
#define X86_CPU(obj) \
@@ -50,7 +53,7 @@ typedef struct X86CPUModel X86CPUModel;
*
* An x86 CPU model or family.
*/
-typedef struct X86CPUClass {
+struct X86CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -72,8 +75,7 @@ typedef struct X86CPUClass {
DeviceRealize parent_realize;
DeviceUnrealize parent_unrealize;
DeviceReset parent_reset;
-} X86CPUClass;
+};
-typedef struct X86CPU X86CPU;
#endif
diff --git a/target/i386/sev.c b/target/i386/sev.c
index de4818d..d452e73 100644
--- a/target/i386/sev.c
+++ b/target/i386/sev.c
@@ -28,12 +28,13 @@
#include "sysemu/runstate.h"
#include "trace.h"
#include "migration/blocker.h"
+#include "qom/object.h"
#define TYPE_SEV_GUEST "sev-guest"
+typedef struct SevGuestState SevGuestState;
#define SEV_GUEST(obj) \
OBJECT_CHECK(SevGuestState, (obj), TYPE_SEV_GUEST)
-typedef struct SevGuestState SevGuestState;
/**
* SevGuestState:
diff --git a/target/lm32/cpu-qom.h b/target/lm32/cpu-qom.h
index bdedb37..2c0654b 100644
--- a/target/lm32/cpu-qom.h
+++ b/target/lm32/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_LM32_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_LM32_CPU "lm32-cpu"
+typedef struct LM32CPU LM32CPU;
+typedef struct LM32CPUClass LM32CPUClass;
#define LM32_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
#define LM32_CPU(obj) \
@@ -38,15 +41,14 @@
*
* A LatticeMico32 CPU model.
*/
-typedef struct LM32CPUClass {
+struct LM32CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} LM32CPUClass;
+};
-typedef struct LM32CPU LM32CPU;
#endif
diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 88b11b6..3b199be 100644
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_M68K_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_M68K_CPU "m68k-cpu"
+typedef struct M68kCPU M68kCPU;
+typedef struct M68kCPUClass M68kCPUClass;
#define M68K_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(M68kCPUClass, (klass), TYPE_M68K_CPU)
#define M68K_CPU(obj) \
@@ -38,15 +41,14 @@
*
* A Motorola 68k CPU model.
*/
-typedef struct M68kCPUClass {
+struct M68kCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} M68kCPUClass;
+};
-typedef struct M68kCPU M68kCPU;
#endif
diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index 053ba44..564fa18 100644
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_MICROBLAZE_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
+typedef struct MicroBlazeCPU MicroBlazeCPU;
+typedef struct MicroBlazeCPUClass MicroBlazeCPUClass;
#define MICROBLAZE_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
#define MICROBLAZE_CPU(obj) \
@@ -38,15 +41,14 @@
*
* A MicroBlaze CPU model.
*/
-typedef struct MicroBlazeCPUClass {
+struct MicroBlazeCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} MicroBlazeCPUClass;
+};
-typedef struct MicroBlazeCPU MicroBlazeCPU;
#endif
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 9d0df6c..3a5fd95 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -21,6 +21,7 @@
#define QEMU_MIPS_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#ifdef TARGET_MIPS64
#define TYPE_MIPS_CPU "mips64-cpu"
@@ -28,6 +29,8 @@
#define TYPE_MIPS_CPU "mips-cpu"
#endif
+typedef struct MIPSCPU MIPSCPU;
+typedef struct MIPSCPUClass MIPSCPUClass;
#define MIPS_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
#define MIPS_CPU(obj) \
@@ -42,7 +45,7 @@
*
* A MIPS CPU model.
*/
-typedef struct MIPSCPUClass {
+struct MIPSCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -50,8 +53,7 @@ typedef struct MIPSCPUClass {
DeviceRealize parent_realize;
DeviceReset parent_reset;
const struct mips_def_t *cpu_def;
-} MIPSCPUClass;
+};
-typedef struct MIPSCPU MIPSCPU;
#endif
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index 455553b..af4d6ab 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -21,6 +21,7 @@
#define MOXIE_CPU_H
#include "exec/cpu-defs.h"
+#include "qom/object.h"
#define MOXIE_EX_DIV0 0
#define MOXIE_EX_BAD 1
@@ -50,6 +51,8 @@ typedef struct CPUMoxieState {
#define TYPE_MOXIE_CPU "moxie-cpu"
+typedef struct MoxieCPU MoxieCPU;
+typedef struct MoxieCPUClass MoxieCPUClass;
#define MOXIE_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(MoxieCPUClass, (klass), TYPE_MOXIE_CPU)
#define MOXIE_CPU(obj) \
@@ -63,14 +66,14 @@ typedef struct CPUMoxieState {
*
* A Moxie CPU model.
*/
-typedef struct MoxieCPUClass {
+struct MoxieCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} MoxieCPUClass;
+};
/**
* MoxieCPU:
@@ -78,14 +81,14 @@ typedef struct MoxieCPUClass {
*
* A Moxie CPU.
*/
-typedef struct MoxieCPU {
+struct MoxieCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUMoxieState env;
-} MoxieCPU;
+};
void moxie_cpu_do_interrupt(CPUState *cs);
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 4dddf9c..7162cbd 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -23,6 +23,7 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
+#include "qom/object.h"
typedef struct CPUNios2State CPUNios2State;
#if !defined(CONFIG_USER_ONLY)
@@ -31,6 +32,8 @@ typedef struct CPUNios2State CPUNios2State;
#define TYPE_NIOS2_CPU "nios2-cpu"
+typedef struct Nios2CPU Nios2CPU;
+typedef struct Nios2CPUClass Nios2CPUClass;
#define NIOS2_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(Nios2CPUClass, (klass), TYPE_NIOS2_CPU)
#define NIOS2_CPU(obj) \
@@ -44,14 +47,14 @@ typedef struct CPUNios2State CPUNios2State;
*
* A Nios2 CPU model.
*/
-typedef struct Nios2CPUClass {
+struct Nios2CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} Nios2CPUClass;
+};
#define TARGET_HAS_ICE 1
@@ -174,7 +177,7 @@ struct CPUNios2State {
*
* A Nios2 CPU.
*/
-typedef struct Nios2CPU {
+struct Nios2CPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -191,7 +194,7 @@ typedef struct Nios2CPU {
uint32_t reset_addr;
uint32_t exception_addr;
uint32_t fast_tlb_miss_addr;
-} Nios2CPU;
+};
void nios2_tcg_init(void);
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index f37a52e..ab0dd55 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -22,12 +22,15 @@
#include "exec/cpu-defs.h"
#include "hw/core/cpu.h"
+#include "qom/object.h"
/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */
struct OpenRISCCPU;
#define TYPE_OPENRISC_CPU "or1k-cpu"
+typedef struct OpenRISCCPU OpenRISCCPU;
+typedef struct OpenRISCCPUClass OpenRISCCPUClass;
#define OPENRISC_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(OpenRISCCPUClass, (klass), TYPE_OPENRISC_CPU)
#define OPENRISC_CPU(obj) \
@@ -42,14 +45,14 @@ struct OpenRISCCPU;
*
* A OpenRISC CPU model.
*/
-typedef struct OpenRISCCPUClass {
+struct OpenRISCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} OpenRISCCPUClass;
+};
#define TARGET_INSN_START_EXTRA_WORDS 1
@@ -305,14 +308,14 @@ typedef struct CPUOpenRISCState {
*
* A OpenRISC CPU.
*/
-typedef struct OpenRISCCPU {
+struct OpenRISCCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUOpenRISCState env;
-} OpenRISCCPU;
+};
void cpu_openrisc_list(void);
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 000c7d4..017f0ef 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -21,6 +21,7 @@
#define QEMU_PPC_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#ifdef TARGET_PPC64
#define TYPE_POWERPC_CPU "powerpc64-cpu"
@@ -28,6 +29,8 @@
#define TYPE_POWERPC_CPU "powerpc-cpu"
#endif
+typedef struct PowerPCCPU PowerPCCPU;
+typedef struct PowerPCCPUClass PowerPCCPUClass;
#define POWERPC_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
#define POWERPC_CPU(obj) \
@@ -35,7 +38,6 @@
#define POWERPC_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
-typedef struct PowerPCCPU PowerPCCPU;
typedef struct CPUPPCState CPUPPCState;
typedef struct ppc_tb_t ppc_tb_t;
typedef struct ppc_dcr_t ppc_dcr_t;
@@ -159,7 +161,7 @@ typedef struct PPCHash64Options PPCHash64Options;
*
* A PowerPC CPU model.
*/
-typedef struct PowerPCCPUClass {
+struct PowerPCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -197,7 +199,7 @@ typedef struct PowerPCCPUClass {
int (*check_pow)(CPUPPCState *env);
int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
bool (*interrupts_big_endian)(PowerPCCPU *cpu);
-} PowerPCCPUClass;
+};
#ifndef CONFIG_USER_ONLY
typedef struct PPCTimebase {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 3c4e1b3..1c6fbfc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -23,6 +23,7 @@
#include "qemu/int128.h"
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
+#include "qom/object.h"
#define TCG_GUEST_DEFAULT_MO 0
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 383808b..ff86613 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -24,6 +24,7 @@
#include "hw/registerfields.h"
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
+#include "qom/object.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -231,6 +232,8 @@ struct CPURISCVState {
QEMUTimer *timer; /* Internal timer */
};
+typedef struct RISCVCPU RISCVCPU;
+typedef struct RISCVCPUClass RISCVCPUClass;
#define RISCV_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
#define RISCV_CPU(obj) \
@@ -245,13 +248,13 @@ struct CPURISCVState {
*
* A RISCV CPU model.
*/
-typedef struct RISCVCPUClass {
+struct RISCVCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} RISCVCPUClass;
+};
/**
* RISCVCPU:
@@ -259,7 +262,7 @@ typedef struct RISCVCPUClass {
*
* A RISCV CPU.
*/
-typedef struct RISCVCPU {
+struct RISCVCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
@@ -292,7 +295,7 @@ typedef struct RISCVCPU {
bool mmu;
bool pmp;
} cfg;
-} RISCVCPU;
+};
static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
{
diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 9054762..dd96469 100644
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -20,12 +20,14 @@
#define RX_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_RX_CPU "rx-cpu"
#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n")
typedef struct RXCPU RXCPU;
+typedef struct RXCPUClass RXCPUClass;
#define RX_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU)
#define RX_CPU(obj) \
@@ -40,14 +42,14 @@ typedef struct RXCPU RXCPU;
*
* A RX CPU model.
*/
-typedef struct RXCPUClass {
+struct RXCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} RXCPUClass;
+};
#define CPUArchState struct CPURXState
diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 1630818..13f1f26 100644
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -21,9 +21,12 @@
#define QEMU_S390_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_S390_CPU "s390x-cpu"
+typedef struct S390CPU S390CPU;
+typedef struct S390CPUClass S390CPUClass;
#define S390_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(S390CPUClass, (klass), TYPE_S390_CPU)
#define S390_CPU(obj) \
@@ -50,7 +53,7 @@ typedef enum cpu_reset_type {
*
* An S/390 CPU model.
*/
-typedef struct S390CPUClass {
+struct S390CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -64,9 +67,8 @@ typedef struct S390CPUClass {
DeviceReset parent_reset;
void (*load_normal)(CPUState *cpu);
void (*reset)(CPUState *cpu, cpu_reset_type type);
-} S390CPUClass;
+};
-typedef struct S390CPU S390CPU;
typedef struct CPUS390XState CPUS390XState;
#endif
diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 72a63f3..bf71c0f 100644
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -21,6 +21,7 @@
#define QEMU_SUPERH_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_SUPERH_CPU "superh-cpu"
@@ -28,6 +29,8 @@
#define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r")
#define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785")
+typedef struct SuperHCPU SuperHCPU;
+typedef struct SuperHCPUClass SuperHCPUClass;
#define SUPERH_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
#define SUPERH_CPU(obj) \
@@ -45,7 +48,7 @@
*
* A SuperH CPU model.
*/
-typedef struct SuperHCPUClass {
+struct SuperHCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -56,8 +59,7 @@ typedef struct SuperHCPUClass {
uint32_t pvr;
uint32_t prr;
uint32_t cvr;
-} SuperHCPUClass;
+};
-typedef struct SuperHCPU SuperHCPU;
#endif
diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 8b4d33c..b7cc81e 100644
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -21,6 +21,7 @@
#define QEMU_SPARC_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#ifdef TARGET_SPARC64
#define TYPE_SPARC_CPU "sparc64-cpu"
@@ -28,6 +29,8 @@
#define TYPE_SPARC_CPU "sparc-cpu"
#endif
+typedef struct SPARCCPU SPARCCPU;
+typedef struct SPARCCPUClass SPARCCPUClass;
#define SPARC_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(SPARCCPUClass, (klass), TYPE_SPARC_CPU)
#define SPARC_CPU(obj) \
@@ -43,7 +46,7 @@ typedef struct sparc_def_t sparc_def_t;
*
* A SPARC CPU model.
*/
-typedef struct SPARCCPUClass {
+struct SPARCCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -51,8 +54,7 @@ typedef struct SPARCCPUClass {
DeviceRealize parent_realize;
DeviceReset parent_reset;
sparc_def_t *cpu_def;
-} SPARCCPUClass;
+};
-typedef struct SPARCCPU SPARCCPU;
#endif
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index 193b6bb..d6cc1d2 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -21,6 +21,7 @@
#define TILEGX_CPU_H
#include "exec/cpu-defs.h"
+#include "qom/object.h"
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
@@ -98,6 +99,8 @@ typedef struct CPUTLGState {
#define TYPE_TILEGX_CPU "tilegx-cpu"
+typedef struct TileGXCPU TileGXCPU;
+typedef struct TileGXCPUClass TileGXCPUClass;
#define TILEGX_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
#define TILEGX_CPU(obj) \
@@ -112,14 +115,14 @@ typedef struct CPUTLGState {
*
* A Tile-Gx CPU model.
*/
-typedef struct TileGXCPUClass {
+struct TileGXCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} TileGXCPUClass;
+};
/**
* TileGXCPU:
@@ -127,14 +130,14 @@ typedef struct TileGXCPUClass {
*
* A Tile-GX CPU.
*/
-typedef struct TileGXCPU {
+struct TileGXCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUNegativeOffsetState neg;
CPUTLGState env;
-} TileGXCPU;
+};
/* TILE-Gx memory attributes */
diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index cd819e6..cef466d 100644
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -19,10 +19,13 @@
#define QEMU_TRICORE_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_TRICORE_CPU "tricore-cpu"
+typedef struct TriCoreCPU TriCoreCPU;
+typedef struct TriCoreCPUClass TriCoreCPUClass;
#define TRICORE_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(TriCoreCPUClass, (klass), TYPE_TRICORE_CPU)
#define TRICORE_CPU(obj) \
@@ -30,15 +33,14 @@
#define TRICORE_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(TriCoreCPUClass, (obj), TYPE_TRICORE_CPU)
-typedef struct TriCoreCPUClass {
+struct TriCoreCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
DeviceReset parent_reset;
-} TriCoreCPUClass;
+};
-typedef struct TriCoreCPU TriCoreCPU;
#endif /* QEMU_TRICORE_CPU_QOM_H */
diff --git a/target/unicore32/cpu-qom.h b/target/unicore32/cpu-qom.h
index 7dd0451..6a1cb1c 100644
--- a/target/unicore32/cpu-qom.h
+++ b/target/unicore32/cpu-qom.h
@@ -12,9 +12,12 @@
#define QEMU_UC32_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_UNICORE32_CPU "unicore32-cpu"
+typedef struct UniCore32CPU UniCore32CPU;
+typedef struct UniCore32CPUClass UniCore32CPUClass;
#define UNICORE32_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(UniCore32CPUClass, (klass), TYPE_UNICORE32_CPU)
#define UNICORE32_CPU(obj) \
@@ -28,14 +31,13 @@
*
* A UniCore32 CPU model.
*/
-typedef struct UniCore32CPUClass {
+struct UniCore32CPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
-} UniCore32CPUClass;
+};
-typedef struct UniCore32CPU UniCore32CPU;
#endif
diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 3ea93ce..cd9f31d 100644
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -30,9 +30,12 @@
#define QEMU_XTENSA_CPU_QOM_H
#include "hw/core/cpu.h"
+#include "qom/object.h"
#define TYPE_XTENSA_CPU "xtensa-cpu"
+typedef struct XtensaCPU XtensaCPU;
+typedef struct XtensaCPUClass XtensaCPUClass;
#define XTENSA_CPU_CLASS(class) \
OBJECT_CLASS_CHECK(XtensaCPUClass, (class), TYPE_XTENSA_CPU)
#define XTENSA_CPU(obj) \
@@ -50,7 +53,7 @@ typedef struct XtensaConfig XtensaConfig;
*
* An Xtensa CPU model.
*/
-typedef struct XtensaCPUClass {
+struct XtensaCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
@@ -59,8 +62,7 @@ typedef struct XtensaCPUClass {
DeviceReset parent_reset;
const XtensaConfig *config;
-} XtensaCPUClass;
+};
-typedef struct XtensaCPU XtensaCPU;
#endif