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authorTao Xu <tao3.xu@intel.com>2018-12-27 10:43:03 +0800
committerEduardo Habkost <ehabkost@redhat.com>2019-01-28 15:51:54 -0200
commitb0a1980384fc265d91de7e09aa5fe531a69e6288 (patch)
tree21dd6e076bc8ed884cac674b3adba40ca1bac7de /target
parent5f39a91dbd9a186edb999afd4d17524f4b1da14f (diff)
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i386: Update stepping of Cascadelake-Server
Update the stepping from 5 to 6, in order that the Cascadelake-Server CPU model can support AVX512VNNI and MSR based features exposed by ARCH_CAPABILITIES. Signed-off-by: Tao Xu <tao3.xu@intel.com> Message-Id: <20181227024304.12182-2-tao3.xu@intel.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Diffstat (limited to 'target')
-rw-r--r--target/i386/cpu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 2f54125..43df813 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -2503,7 +2503,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
.vendor = CPUID_VENDOR_INTEL,
.family = 6,
.model = 85,
- .stepping = 5,
+ .stepping = 6,
.features[FEAT_1_EDX] =
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |