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authorBruno Larsen (billionai) <bruno.larsen@eldorado.org.br>2021-11-04 09:37:14 -0300
committerDavid Gibson <david@gibson.dropbear.id.au>2021-11-09 10:32:53 +1100
commitaa4592fab7cc28ef230ecab5c7e5b4d3936917ce (patch)
tree3d3a785475ee913b1b34543f072b2d6589b19d61 /target
parent6166fced10f635b789807df23af70037031ea56d (diff)
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target/ppc: implemented XXSPLTI32DX
Implemented XXSPLTI32DX emulation using decodetree Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20211104123719.323713-21-matheus.ferst@eldorado.org.br> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target')
-rw-r--r--target/ppc/insn64.decode11
-rw-r--r--target/ppc/translate/vsx-impl.c.inc17
2 files changed, 28 insertions, 0 deletions
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3e..134bc60 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
+# Format 8RR:D
+%8rr_si 32:s16 0:16
+%8rr_xt 16:1 21:5
+&8RR_D_IX xt ix si
+@8RR_D_IX ...... .. .... .. .. ................ \
+ ...... ..... ... ix:1 . ................ \
+ &8RR_D_IX si=%8rr_si xt=%8rr_xt
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -156,3 +164,6 @@ PLXVP 000001 00 0--.-- .................. \
111010 ..... ..... ................ @8LS_D_TSXP
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+
+XXSPLTI32DX 000001 01 0000 -- -- ................ \
+ 100000 ..... 000 .. ................ @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ad25a0d..360593a 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,23 @@ static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
return true;
}
+static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
+{
+ TCGv_i32 imm;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ imm = tcg_constant_i32(a->si);
+
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
+ tcg_gen_st_i32(imm, cpu_env,
+ offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;