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authorBin Meng <bin.meng@windriver.com>2020-09-01 09:39:10 +0800
committerAlistair Francis <alistair.francis@wdc.com>2020-09-09 15:54:19 -0700
commita47ef6e93ab2ca1db8d5ecb61fda3c41f926a26b (patch)
tree00c66845ba4693643cd3bd41f190908b781543fd /target
parentce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c (diff)
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hw/riscv: clint: Avoid using hard-coded timebase frequency
At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-16-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
-rw-r--r--target/riscv/cpu.h6
-rw-r--r--target/riscv/cpu_helper.c4
-rw-r--r--target/riscv/csr.c4
3 files changed, 9 insertions, 5 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0d1728a..65daa73 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -219,7 +219,8 @@ struct CPURISCVState {
pmp_table_t pmp_state;
/* machine specific rdtime callback */
- uint64_t (*rdtime_fn)(void);
+ uint64_t (*rdtime_fn)(uint32_t);
+ uint32_t rdtime_fn_arg;
/* True if in debugger mode. */
bool debugger;
@@ -350,7 +351,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+ uint32_t arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 0058806..f4c4111 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -276,9 +276,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
-void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
+void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
+ uint32_t arg)
{
env->rdtime_fn = fn;
+ env->rdtime_fn_arg = arg;
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 200001d..26ae347 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -351,7 +351,7 @@ static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
return -RISCV_EXCP_ILLEGAL_INST;
}
- *val = env->rdtime_fn() + delta;
+ *val = env->rdtime_fn(env->rdtime_fn_arg) + delta;
return 0;
}
@@ -364,7 +364,7 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
return -RISCV_EXCP_ILLEGAL_INST;
}
- *val = (env->rdtime_fn() + delta) >> 32;
+ *val = (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32;
return 0;
}
#endif